Method for forming self-aligned selective silicide layer using c

Details Method for forming self-aligned selective silicide layer using c Method for forming self-aligned selective silicide layer using c

1999-04-26

2000-11-14

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438303, 438592, 438634, 438655, 438664, 438682, 438253, H01L 214763

Patent

active

061469947

ABSTRACT:
A semiconductor device including a first area where a silicide layer is formed only on a gate electrode, and a second area where a silicide layer is formed both on the gate electrode and on source and drain areas is produced by a method wherein a polishing stopper and an oxide layer are sequentially stacked, the gate electrode is exposed in a self-aligned manner, and then a first silicide layer is formed to thereby suppress misalignment in the process of manufacturing a semiconductor device having a fine linear width. In the first area, when first and second insulating layers are stacked and contact holes are formed directly connected to the semiconductor substrate, a second silicide layer is formed at the bottoms of the contact holes, to reduce contact resistance and leakage current.

REFERENCES:
patent: 5026666 (1991-06-01), Hills et al.
patent: 5891785 (1999-04-01), Chang
patent: 6025267 (2000-02-01), Pey et al.

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