Method for forming self-aligned contacts using a hard mask

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

Reexamination Certificate

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Details

C438S597000

Reexamination Certificate

active

06265296

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of self-aligned contacts on semiconductor devices, and more particularly to a method for making self-aligned source/drain contacts on semiconductor devices using a hard mask.
2. Description of the Related Arts
Because the trend of semiconductor manufacturing is toward highly integrated semiconductor devises, the tolerance of the patterning has become stricter. A self-aligned contact which partially overlays the source/drain and the gate electrode is developed to increase the tolerance of mis-patterning and enhance the density of the integrated devises.
Conventional self-aligned contacts are typically fabricated by the following procedures. Referring to
FIG. 1A
, a gate oxide layer
112
, a gate electrode structure
117
consisting of a gate electrode
114
and a gate protecting layer
116
, a lightly doped region
118
, a insulating sidewall spacer
120
on the sidewalls of gate electrode structure
117
, and a heavily doped region
122
are successively fabricated on a semiconductor substrate
110
. Then, an insulating layer
124
is depositing to blanket the substrate
110
and a photoresist
126
is formed on the insulating layer
124
.
Turning to
FIG. 1B
, the conventional self-aligned contact
128
is completed by etching the insulating layer
124
to the gate electrode protecting layer
116
using the photoresist
126
as the mask, and then etching the insulating layer
124
to the heavily doped region using the gate electrode structure
117
and the sidewall spacers
120
together as the mask.
Unfortunately, several problems occurs because of the usage of photoresist as a mask. Photoresist, which is for the most part composed of organic compounds, generates by-products, such as organic polymers in the self-aligned contacts during the etching procedures. That leads to impairment of the devises or the need for additional procedures to remove the by-products. Another problem arises from the thickness of the photoresist, which is up to 5000-7000 Å on average. That results in a high aspect ratio which makes it difficult to define the self-aligned contacts.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to present a method of forming self-aligned contacts which is free of the above problems.
According to the object of the invention, a method of forming self-aligned contacts using a hard mask is provided, which comprises the steps of: providing a semiconductor substrate; forming a gate oxide layer on said semiconductor substrate; forming a gate electrode layer on said gate oxide layer; forming a gate electrode protecting layer on said gate electrode layer; patterning said gate electrode protecting layer and said gate electrode layer, thereby forming gate electrode structures having vertical sidewalls; forming first doped regions in portions of said semiconductor substrate adjacent to said gate electrode structures; forming insulating sidewall spacers on said sidewalls of said gate electrode structures; forming second doped regions in portions of said semiconductor adjacent to said sidewall spacers; forming a blanket insulating layer on said semiconductor substrate; forming a hard mask having openings on said blanket insulating layer, said openings overlaying said first doped regions, said second doped regions and part of said gate electrode structure; etching said blanket insulating layer to said gate electrode protecting layer through said openings; etching said blanker insulating layer to expose said second doped regions using said gate electrode protecting layer and said insulating sidewall spacers as the mask, thereby forming said self-aligned contacts.


REFERENCES:
patent: 4486943 (1984-12-01), Ryden et al.
patent: 5286667 (1994-02-01), Lin et al.
patent: 5352621 (1994-10-01), Kim et al.
patent: 5872063 (1999-02-01), Chao et al.

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