Method for forming self-aligned contacts and local...

Details Method for forming self-aligned contacts and local... Method for forming self-aligned contacts and local...

2001-03-05

2001-10-23

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000

Reexamination Certificate

active

06306713

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to an improved fabrication process for making semiconductor memory devices.
BACKGROUND ART
In general, memory devices such as a Flash electrically erasable programmable read only memory (EEPROM) are known. EEPROMs are a class of nonvolatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling.
Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip), having a heavily doped drain region and a source region embedded therein. The source region further contains a lightly doped deeply diffused region and a more heavily doped shallow diffused region embedded into the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multi-layer structure, commonly referred to as a “stacked gate” structure or word line. The stacked gate structure typically includes: a thin gate dielectric or tunnel oxide layer formed on the surface of substrate overlying the channel region; a polysilicon floating gate overlying the tunnel oxide; an interpoly dielectric overlying the floating gate; and a polysilicon control gate overlying the it interpoly dielectric layer. Additional layers, such as a silicide layer (deposited on the control gate), a poly cap layer (deposited on the gate silicide layer), and a silicon oxynitride layer (deposited on the poly cap layer) may be formed over the control gate. A plurality of Flash EEPROM cells may be formed on a single substrate.
A Flash EEPROM also includes peripheral portions, which typically include input/output circuitry for selectively addressing individual memory cells.
The process of forming Flash EEPROM cells is well known and widely practiced throughout the semiconductor industry. After the formation of the memory cells, electrical connections, commonly known as “contacts”, must be made to connect the stacked gate structure, the source region and the drain regions to other parts of the chip. The contact process starts with the formation of sidewall spacers around the stacked gate structures of each memory cell. A salicidation process is applied to the active region and poly-gate. An etch stop or liner layer, typically a nitride material such as silicon nitride, is then formed over the entire substrate, including the stacked gate structure, using conventional techniques, such as chemical vapor deposition (CVD). A dielectric layer, generally of oxide such as such as boro-phospho-tetra-ethyl-ortho silicate (BPTEOS) or borophosphosilicate glass (BPSG), is then deposited over the etch stop layer. A chemical-mechanical planarization (CMP) process is applied to the wafer and wafer-scale planarization is achieved. A layer of photoresist is then placed over the dielectric layer and is photolithographically processed to form the pattern of contact openings. An anisotropic etch is then used to etch out portions of the dielectric layer to form source and drain contact openings in the oxide layer. The contact openings stop at the source and drain regions in the substrate. The photoresist is then stripped, and a conductive material, such as tungsten, is deposited over the dielectric layer and fills the source and drain contact openings to form so-called “self-aligned contacts” (conductive contacts). The substrate is then subjected to a CMP process, which removes the conductive material above the dielectric layer to form the conductive contacts through a contact CMP process.
For miniaturization, it is desirable to have adjacent word lines as closely together as possible. However, in order to accommodate electrical contacts in the active regions (source and drain) between the stacked gates and avoid electrical shorts between stacked gates and core active areas, wide spacing (separation) between word lines is required. This process significantly increases semiconductor memory core cell size and therefore adversely impacts semiconductor device and memory densities. Moreover, this problem is becoming more critical as separation between adjacent stacked gate structures diminishes with semiconductor technology feature size scaling down to sub-quarter micron level and below.
The above becomes worse at smaller geometries because the core region must be treated differently from the peripheral region. In the core region, it is necessary that the gate contact and source/drain contacts be isolated. In the peripheral region, it is necessary that the gate contact and source/drain contacts be in contact and form local interconnect to increase packing density and device performance.
A solution, which would allow further miniaturization of memory device without adversely affecting device performance has long been sought, but has eluded those skilled in the art. As the demand for higher performance devices and miniaturization continues at a rapid pace in the field of semiconductor, it is becoming more pressing that a solution be found.
DISCLOSURE OF THE INVENTION
The present invention provides a method for shrinking a semiconductor device by processing the core region to form contacts separately in a decoupled process from the peripheral region so the stacked gate structures can be positioned closer together.
The present invention provides a method of manufacturing a semiconductor device in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers and a salicidation process is applied to form salicided source/drain and gate contacts. A stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A chemical-mechanical planarization (CMP) process is applied to the wafer and wafer-scale planarization is achieved. A photoresist contact mask is deposited, processed, and used to form core self-aligned contact openings over the core region so as to expose the multi-layer structure in addition to the source and drain regions while covering the peripheral region. A spacer layer is deposited over the wafer by a conventional CVD process and a spacer etch process is employed to form protective secondary sidewall spacers in the core contact openings over the exposed multi-layer structures. A second photoresist contact mask is deposited, processed, and used to form peripheral local interconnect openings over the peripheral region which the source regions and portions of the plurality of multi-layer structures in the peripheral region while covering the core region. A conductive material is deposited over the dielectric layer and in the core contact and peripheral local interconnect openings and is chemical-mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core and peripheral contact openings.
The above and additional advantages of the present invention will become apparent to, those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5907781 (1999-05-01), Chen et al.
patent: 6136649 (2000-10-01), Hui et al.
patent: 6255584 (2001-05-01), Sun et al.
U.S. application No. 09/685,972, Hu et al., filed Oct. 10, 2000.
U.S. application No. 09/685,968, Kinoshita et al., filed Oct. 10, 2000.
U.S. application No. 09/502,628, Wang et al., filed Feb. 11, 2000.
U.S. application No. 09/502,153, Wang et al., filed Feb. 11, 2000.
U.S. application No. 09/502,375, Kinoshita et al., Feb. 11, 2000.
U.S. application No. 09/502,163, Wang et al., filed Feb. 11, 2000.

Affiliated with

Also associated with

Rating

Method for forming self-aligned contacts and local... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming self-aligned contacts and local..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming self-aligned contacts and local... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2560441