Method for forming self aligned contacts

Details Method for forming self aligned contacts Method for forming self aligned contacts

2001-08-27

2002-11-26

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S233000, C438S239000, C438S241000, C438S618000, C438S585000, C438S264000

Reexamination Certificate

active

06486016

ABSTRACT:

BACKGROUND
1. Technical Field
A method for forming a self aligned contact, and in particular, a method for forming a self aligned contact which can make an electrical insulation margin increase between a conductive pattern and a contact when fabricating a fine contact of a high integration semiconductor.
2. Description of the Background Art
High integration of semiconductor devices has necessitated studies on new materials for lithography, cell structure and wiring, as well as on the limitation of a property of matter related to the insulation layer. Moreover, as the cell area is being reduced due to high integration of semiconductor devices, it is also inevitable to reduce the contact hole area.
Misalignment of a mask frequently exposes a peripheral structure such as a gate electrode or a bit line, which causes contact to be made between a gate electrode and a storage electrode, and a bit line and a storage electrode, respectively, thus resulting in low reliability of the memory device.
Hence, studies have been made to develop methods of achieving minimization of a contact hole without having to expose peripheral structure due to misalignment of a mask, among which is a Self Aligned Contact Method.
In the said Self Aligned Contact Method, only the contact area can be opened by controlling the amount of etching by using the prominence and depression of the semiconductor substrate. Since this method is capable of obtaining a contact of various sizes depending on the height of the peripheral structure, thickness of the insulation material on which a contact is to be formed, and the etching method, it is useful for fabricating semiconductor devices which are being minimized due to high integration.
For example, the execution of the Self Aligned Contact Method on a substrate on which the word line and bit line is formed will be described as follows.
FIGS. 1
a
to
1
c
are views illustrating processes for explaining the self aligned contact method in accordance with the conventional art.
As shown in
FIG. 1
a,
the word line or the bit line is formed on the semiconductor substrate
10
having a predetermined lower structure. At this time, a doped polysilicon layer
12
and a tungsten layer
14
construct the word line or the bit line. A hard mask
16
is formed on the tungsten layer
14
and a spacer
18
made of insulating materials is formed on the sidewall of the tungsten layer
14
. An etch barrier layer
11
is formed on the surface of the substrate, between the spacers. An oxide thin layer
20
and an inter-layer insulating layer (not shown) are formed on the entire surface of the substrate.
Thereafter, as shown in
FIG. 1
b,
the interlayer insulating layer and the oxide thin layer between the spacers
18
are etched by executing a photolithography process using the self aligned contact mask.
Thereafter, as shown in
FIG. 1
c,
the etch barrier layer
11
between the spacers
18
is removed and then the self aligned contact is formed, thereby exposing the surface of the substrate.
On the other hand, as the degree of integration of semiconductor processes become higher, the design rule of the devices is being reduced, a fabricating method for exposing the substrate by using a mask of T-type or bar-type is used in a contact fabricating process in order to obtain a sufficient space. In order to use such an etching technology, in the contact fabricating method, an electrical insulation between the line and the contact must be achieved by minimizing damage of the hard mask and the spacer surrounding the word line and the bit line.
When the device isolation region is exposed in an etching process for the self aligned contact, the leakage current characteristic become deteriorated and so generally the etch barrier layer is added before depositing the interlayer insulating layer. So, the etch barrier layer must be removed in order to open the active region of the substrate in the contact fabricating process.
However, when removing the etch barrier layer between the spacers, in case of executing an over etch, the over etch of the hard mask
16
′ and the spacer by which the word line or the bit line are surrounded occurs and so an interlayer insulation characteristic become deteriorated.
So, if the thickness of the hard mask is increased, it is difficult to form a pattern of the word line and, thereafter, when filling a gap of the self aligned contact region, a void is generated.
In addition, when the oxidation material is used as an etch barrier layer and the nitride material is used as a hard mask and a spacer, in etching the oxide layer, since the gas for generating much polymer is combined in order to obtain high selectivity to the nitride layer, the bottom part of the spacer is etched incompletely, as a reference numeral F, so it is difficult to secure the contact area.
SUMMARY OF THE DISCLOSURE
Accordingly, a method for forming the self aligned contact is disclosed in which: an uneven buffer layer is thickly formed on the upper surface of the line and thinly formed on the substrate by depositing insulation material having a bad step coverage (i.e., good coverage between the steps but poor or negligible coverage of the sides and tops of the steps), and thereafter the uneven buffer layer is etched and the substrate is opened, so that since the hard mask of the line part is protected by the uneven buffer layer deposited thickly, damage caused by the etching process can be reduced, thereby enhancing the insulating characteristic between the line and the contact.
In order to achieve the above-described aspect of the disclosure, a method comprises: forming a conductive line and a hard mask on a structure of a semiconductor substrate; forming spacers constructed by an insulation material on the sidewalls of the conductive line and the hard mask; forming an interlayer insulating layer on the resultant material and then etching the interlayer insulating layer at the contact part; forming an etching barrier layer on the surface of the substrate between the spacers; forming an uneven buffer layer on the resultant material, the uneven buffer deposited thickly on the hard mask and thinly on the etching barrier layer by using a material having inconsistent coverage; and forming a self aligned contact by sequentially etching the uneven buffer layer and the etching barrier layer and then opening the surface of the substrate between the spacers.


REFERENCES:
patent: 5019525 (1991-05-01), Virkus et al.
patent: 5104822 (1992-04-01), Butler
patent: 5631179 (1997-05-01), Sung et al.
patent: 6015730 (2000-01-01), Wang et al.
patent: 6165880 (2000-12-01), Yaung et al.
patent: 6335285 (2002-01-01), Chun et al.
patent: 6350665 (2002-02-01), Jin et al.

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