Method for forming self-aligned contact with liner

Details Method for forming self-aligned contact with liner Method for forming self-aligned contact with liner

2000-09-05

2001-10-23

Zarabian, Amir (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S639000, C438S669000, C438S672000

Reexamination Certificate

active

06306759

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of integrated circuits, and more particularly to a method for forming self-aligned contacts (SAC) utilizing dielectric liner for device improvement.
2. Description of the Prior Art
DRAM is a major volatile memory. Because the integration requirement of the semiconductor device is increasingly higher, the combination of logic and DRAM is widely applied to wafers, and the bit-line contact and the node contact are both designed to be self-aligned contacts (SAC) so as to reduce the size of the wafer.
However, there are several problems associated with the conventional SAC process. These problems are best understood by referring to the prior art shown in FIGS.
1
(
a
) through
1
(
c
) in which a sequence of schematic cross-sectional views is shown of the process steps. As shown in FIG.
1
(
a
), SAC process starts by providing a semiconductor substrate
100
with a plurality of defined poly structures
102
forming thereon. Masking by these structures
102
, lightly doped drain (LDD) implantation may then be proceeded onto the substrate
100
to form LDD regions
132
. After the implantation, these poly structures
102
seek protection by means of spacer formation. The spacers
104
shown in the figure are constructed typically by depositing a layer of dielectric and then etched to form. Silicon nitride is preferred for use as such spacers for the material possesses reasonably good oxidation resistance. However, other adequate dielectrics may also be chosen. The etching of the spacers is usually done by plasma. In addition to spacer protection, a cap layer
105
is often used to top of the poly
1
structure as an “etch stop”. The preferred etch “stop” material currently used for semiconductor fabrication is silicon nitride.
Followed by the spacer (and cap layer) formation, an oxide layer
106
is formed over the substrate
100
by, for example, chemical vapor deposition (CVD). The preferred oxide layer is silicon dioxide, or other oxide such as, BPSG. Next, conventional phtolithographic techniques are applied to pattern the oxide layer
106
and etch open anisotropicly contact openings
110
along the spacers
104
in a self-aligned manner. However, the etch back of the CVD oxide layer
106
to the silicon nitride (spacer
104
and cap
105
) is not selective enough to achieve perfect protection of the device, especially at disadvantagous area such as the cap corners which etchants may attack directly. Thus misalignment of the resist
108
patterning often results in comer loss of the protecting nitride (comer of spacer
104
and cap
105
) during the contact opening formation, and recess areas such as
112
indicated in FIG. (
1
b
) are often found during the SAC process. Since it is getting more difficult to control pattern aligning and the etching back within the required processing tolerances as the device size keeps on shrinking, the nitride corner loss becomes a major concern for appropriate electrical isolation between contacts and conducting lines lying underneath. In addition, the etching back of the oxide layer
106
is frequently done by plasma. Inevitable substrate damage induced by the plasma etching could raise another issue for the conventional SAC process.
After the etching back of the oxide layer
106
, the device is further treated with wet chemical to complete the contact opening formation. Unfortunately, a phenomena called kissing plug is sometimes observed during this step. Since the wet deep process may affect critical dimensions of the structures, the adjacent contacts may be so enlarged that they touch one another and result in possible plug-plug short of the device.
Once the contact openings
110
are formed, the photoresist layer
108
, usually made of polymeric material, is stripped off. Then implantation of the substrate
100
may be further done through the contact openings
110
to form doping regions
134
. Together with the previously doped LDD regions
132
, one resulting implantation profile is illustrated in FIG.
1
(
c
). Finally contact openings
110
are filled with a conductive plug to complete the SAC process.
As the density of DRAM chips progress to giga-bit levels, the area of the DRAM cell decreases to 0.17 micrometers or less. Without modifications of the process, the conventional SAC procedure could cause, by experience, over 90% failure of the product for manufacturing 0.19-micron or less cells. To accommodate the reduced area of the DRAM cell, more aggressive design rules have to be used. Thus there is a strong need to provide an improved method for forming self-aligned contacts.
SUMMARY OF THE INVENTION
In view of the foregoing deficiencies and design considerations, a dielectric liner is utilized to enhance contact insulation so as to improve device reliability. Optional contact implantation before and after the liner formation can be added to further optimize device performance.
In one embodiment, the dielectric liner is formed over a conventional contact opening before the contact plug is filled in. Additional implantation of the substrate is done after the liner formation to enhance the doping profile of the substrate between the adjacent conductive structures. In addition to the liner formation and doping profile enhancement of the device, in another embodiment of the invention, an un-etched dielectric protection layer is used to replace conventional spacers (and the cap layer can then be eliminated) to improve comer strength and provide substrate protection of the device.
The proposed SAC contact process is advantageous over the conventional one. First of all, spacer etching at the cell area can be eliminated so as to reduce possible plasma damages and simplify process steps. Secondly, the presence of a SAC liner reduces the risks of contact CD (critical dimension) gain and possible plug-plug short during post-etching wet chemical treatment. Thirdly, contact implantation can be further treated after contact liner formation to optimize the cell devices. And most important of all, the present invention provides solid SAC contact isolation to adapt required design rules so that product reliability could now catch up with the advancement of device integration.


REFERENCES:
patent: 6025255 (2000-02-01), Chen et al.
patent: 6078073 (2000-06-01), Habu et al.
patent: 6103608 (2000-08-01), Jen et al.
patent: 6194784 (2001-02-01), Parat et al.
patent: 6204134 (2001-03-01), Shih
patent: 6228731 (2001-05-01), Liaw et al.

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