Method for forming self-aligned contact

Details Method for forming self-aligned contact Method for forming self-aligned contact

1999-08-10

2001-06-19

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S261000, C438S263000

Reexamination Certificate

active

06248654

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming a self-aligned contact in a semiconductor device.
2. Description of the Related Art
As the integration level of dynamic random access memory (DRAM) devices increases, the minimum feature size of elements and the space occupied by the elements are reduced. Misalignment may occur during the photo process used to form contact holes. As a result, the insulating layer etching process used to form the contact holes may expose a lower conductive layer, generating a short between the exposed conductive layer and a conductive layer filling a contact hole. In order to solve these problems, a self-aligned contact (referred to below as a “SAC”) is suggested. If the minimum feature size of the elements is too small to secure a misalignment margin in the photo process, the SAC process should be used. However, the SAC process has a few problems, as described below.
Referring to
FIG. 1
, gate lines
14
are grown on a semiconductor substrate in the Y-direction. An active region
10
b
, which is surrounded by a device isolation region
12
, is formed to the X-direction (i.e., perpendicular to the gate lines
14
). An interlayer insulating film is formed on the semiconductor substrate and the gate lines
14
, and a bar-type photoresist pattern
20
is formed on the interlayer insulating film. Using the photoresist pattern
20
as a mask, the interlayer insulating film is etched.
Referring to
FIG. 2A
, an active region
10
b
and an inactive region
12
are shown on a semiconductor substrate
10
a
. The device isolation region
12
is formed on a gate oxide layer (not shown) over semiconductor substrate
10
a
. A conductive layer for a gate electrode and an insulating layer for a gate mask are sequentially formed. Using a mask (not shown), the insulating layer is etched to form a gate mask
14
b
. Using the gate mask
14
b
, the conductive layer is etched to form a gate electrode
14
a
. The gate mask may be made of silicon nitride.
Referring to
FIG. 2B
, a silicon nitride layer
14
c
and an interlayer insulating film
16
are sequentially formed on an overall surface of the semiconductor substrate
10
a
including the gate electrode
14
a
and gate mask
14
b
. The interlayer insulating film
16
is planarized through a chemical mechanical polishing (CMP) process. The silicon nitride layer
14
c
serves as an etch-stop layer.
A photoresist layer is patterned on the interlayer insulating film
16
, so that a photoresist pattern (not shown) is formed. Using the photoresist pattern as a mask, the interlayer insulating film
16
is etched down to a top surface of the silicon nitride layer
14
c
in the regions not covered by the photoresist pattern, as shown in FIG.
2
C. The silicon nitride layer
14
c
is anisotropically etched down to a top surface of the active region
10
b
, so that a silicon nitride layer spacer
14
c
is formed on both sidewalls of the gate electrode
14
a
and the gate mask
14
b
. After formation of the gate electrode
14
a
and the spacer
14
c
, an impurity ion is implanted into the active region
10
b
, so that a source/drain region (not shown) is formed. Then, the photoresist pattern is removed.
Referring to
FIG. 2D
, a conductive layer (for example, a polysilicon layer) is formed on the overall surface of the semiconductor substrate
10
a
including the spacers
14
c
and gate masks
14
b
, filling the gaps between the gates
14
. The conductive layer is then planarized using a CMP process. During this process, the gate mask
14
b
serves as an etch-stop layer. Thus, a contact plug
18
is formed using the above SAC process.
However, this prior art method may create problems as follows:
(1) In order to expose the semiconductor substrate
10
a
where the contact plug
18
is formed, the interlayer insulating layer
16
and the nitride layer
14
c
may be overetched resulting in imperfect formation of the silicon nitride spacer
14
c
and exposing an edge of the gate electrode
14
a
. Consequently, a short may occur between the edge of the gate electrode
14
a
and a pad formed during subsequent processing;
(2) If the gate mask
14
b
and the silicon nitride layer
14
c
are made thick enough to accommodate overetching, the space between gates
14
may become too narrow. This narrow space makes filling the space with the interlayer insulating film
16
difficult, resulting in the formation of void regions V, as shown in FIG.
2
B. Because these voids are formed in the direction of the word lines of a DRAM device, conductive areas may be electrically connected via the voids during subsequent pad formation, thereby generating undesirable pad-to-pad bridges; and
(3) Because of its small width, misalignment of the bar-type photoresist pattern
20
may cause problems. If the photoresist pattern
20
is misaligned, it may cover part or all of the interlayer insulating film
16
on the active region
10
b
. Consequently, the contact area between the contact plug
18
to the semiconductor substrate
10
a
may be reduced, increasing contact resistance. In severe cases, there may be no electrical contact between the contact plug
18
and active region
10
b.
SUMMARY OF THE INVENTION
The present invention provides a method for forming a self-aligned contact which may reduce or eliminate pad-to-gate electrode shorts by preventing exposure during etching of the gate electrode. The method of the invention also may reduce or eliminate pad-to-pad bridging by preventing generation of void regions, and may reduce contact resistance by securing enough contact area between a pad and an active region in spite of misalignment of a photoresist pattern.
In accordance with one aspect of the invention there is provided a method of forming a self-aligned contact in a semiconductor device comprising a semiconductor substrate and a plurality of gate lines thereon. The method comprises the steps of forming a conductive layer on an overall surface of the semiconductor substrate including the gate lines, planarization-etching the conductive layer down to a top surface of the gate lines, and etching selected portions of the conductive layer to form a plurality of self-aligned contacts that are electrically separated from one another.
The semiconductor device may comprise a device isolation layer formed on the semiconductor substrate defining an active region and an inactive region, the self-aligned contacts being formed on the active region. Each gate line may comprise a gate electrode, a gate mask, and a gate spacer. The planarization-etching process may be performed using an etch-back process or a chemical mechanical polishing process, and the gate mask may serve as an etch-stop layer in the planarization-etching process. The etching of selected portions of the conductive layer for forming the plurality of self-aligned contacts may be performed using a slope-etch process.
In accordance with another aspect of the invention there is provided a method of forming a contact on a semiconductor substrate comprising a plurality of active regions. The method comprises the steps of forming a plurality of gate lines on the semiconductor substrate, each of the gate lines comprising a gate electrode, a gate mask, and a gate spacer, depositing a conductive layer on the semiconductor substrate and the gate lines to fill spaces between the gate lines, planarization-etching the conductive layer down to a top surface of the gate mask of the gate lines, forming a mask covering the conductive layer aligned over contact formation regions, and etching exposed portions of the conductive layer to form a plurality of self-aligned contacts that are electrically separated from one another.
According to the method, etching of an interlayer insulating film is omitted. Thus, the present invention has advantages as follows:
(1) A spacer may be imperfectly formed, thus exposing the gate electrode so that a pad-to-gate electrode short is generated

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