Method for forming rugged polysilicon capacitor

Details Method for forming rugged polysilicon capacitor Method for forming rugged polysilicon capacitor

1999-07-14

2001-01-09

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S238000, C438S253000, C438S239000, C438S396000, C438S398000, C438S528000, C438S964000

Reexamination Certificate

active

06171904

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming rugged polysilicon capacitance electrodes, that is use in dynamic random access memory processes. And more particularly, the present invention relates to a method for forming rugged polysilicon capacitance electrodes that eventually reduces process time, enhances yield, and saves production costs.
2. Description of the Prior Art
Recently, demand for dynamic random access memory (DRAM) has rapidly increased owing to widespread use of electronic equipment. In particular, it is applied relatively information industry in the computer hardware. In addition to applied information industry, large-scale integration (LSI), very large scale integration (VLSI), and ultra large-scale integration (ULSI) must use greatly dynamic random access memory. In next century, the fabricated technology of the dynamic random access memory (DRAM) is still performed a primary role. Due to electronic, information, and communication product intent to light, thin, short, and quick, which high density and large capacity of the dynamic random access memory with demand is increased.
In dynamic random access memory fabrication, high density and large capacity of the dynamic random access memory is fabricated rugged polysilicon method. This is used hemispherical surface more large surface area than plane, by using increased the capacitor of the dynamic random access memory.
FIG. 1
shows stage
100
placing a semiconductor wafer into low-pressure chemical vapor deposition (LPCVD) reactor and depositing a polysilicon layer. Stage
110
shows first ion implantation in a semiconductor wafer. However, stage
120
uses 1% dilute HF, by using wet etching forming a thin chemical oxide of polysilicon surface. Moreover, stage
130
places a chip into low-pressure chemical vapor deposition (LPCVD) reactor, by using the rugged polysilicon layer to form the rugged polysilicon capacitor. Stage
140
shows second ion implantation in semiconductor wafer. Stage
150
uses wet cleaning for the second time to clean wafer. Finally, stage
160
performs an annealing process at 850° C. temperature. The entire process takes about 1 to 2 days, hence not only wasting time and also resulting in yield reduction due to particle contamination on wafer surface during ion implantation and wafer cleaning outside LPCVD tube.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming rugged polysilicon capacitance electrodes that substantially solves the drawbacks of the conventional way for forming rugged polysilicon capacitance electrodes.
In one objective of the present invention, a method for forming rugged polysilicon capacitance electrodes is provided to reduce the process time. Since the present invention is accomplished within a single LPCVD tube to form the entire structure of rugged polysilicon capacitance electrode, the time required is only 4 to 5 hours. In comparing with 1 to 2 days for the conventional method, a saving of 60 to 80 percent of process time can be achieved. Therefore, an advantage of process time reduction is provided potentially.
Another objective of the present invention, a method for forming rugged polysilicon capacitance electrodes is provided to enhance yield. Since the present invention is accomplished within a single LPCVD tube to form the entire structure of rugged polysilicon capacitance electrode, and unlike the conventional method must enter and exist LPCVD tube for two times. Therefore, an increment of particles adhering to wafers due to the shifting of working areas can be greatly reduced. Hence, results in contamination-free wafers and an enhancement in yield.
A further objective of the present invention, a method for forming rugged polysilicon capacitance electrodes is provided to save production costs. Since the present invention is accomplished within a single LPCVD tube to form the entire structure of rugged polysilicon capacitance electrode, only one ion implantation and one cleaning process are needed. Unlike the conventional method, two sets of ion implantation and cleaning process are required. Therefore, the present invention is accompanied by the advantage of both the reductions in process flow and in production costs.
In accordance with the above objectives, a rapid process for forming rugged polysilicon capacitance electrodes is provided. First of all, a semiconductor wafer is delivered into a LPCVD tube. Herein, a non-doped or doped amorphous silicon layer is deposited on the surface top of electrodes. A rugged polysilicon capacitance is formed on top of the non-doped or doped amorphous silicon layer by using the methods of rising temperature and decreasing pressure. Then, an ion implantation is applied and follows by a wafer cleaning procedure and an annealing process, wherein those procedures are accomplished after the removal of the wafer from LPCVD tube. During the annealing process, the non-doped or doped amorphous silicon layer is transformed into a polysilicon layer under a temperature roughly about 850° C. In particularly, an in-situ phosphorous doped amorphous silicon can be deposited prior to the formation of non-doped amorphous silicon layer, and won't influence the stages that follow.


REFERENCES:
patent: 5856007 (1999-01-01), Sharan et al.
patent: 5937307 (1999-08-01), Jeng et al.
patent: 5937314 (1999-01-01), Ping et al.

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