Method for forming raised source and drain

Details Method for forming raised source and drain Method for forming raised source and drain

1998-11-17

2001-03-13

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S303000, C438S592000, C438S642000, C438S649000, C438S655000, C438S664000, C438S682000

Reexamination Certificate

active

06200867

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains in general to a method for forming raised source and drain regions in a semiconductor transistor device and, more particularly, to a method of forming self-aligned raised source and drain regions in a metal-oxide semiconductor (“MOS”) transistor device.
2. Description of the Related Art
As transistor dimensions in integrated circuits become smaller, the formation of ultra-shallow transistor junctions has become an important consideration in device formation. A mechanism that allows the formation of ultra-shallow junctions is through the formation of raised, or elevated, source and drain regions.
The material that constitutes the raised source and drain regions is generally the same as the device substrate, which in most instances is silicon. The raised source and drain regions may also be used as alternative self-aligned contacts in ultra-large silicon integration (“ULSI”) MOS devices, but they first need to be metalized. A metalized silicon, or silicide, is silicon combined with a metal, and is formed over the source and drain regions. Silicides may be provided as a Group VIII silicide (PtSi, Pd
2
Si, CoSi
2
and NiSi
2
) or as TiSi
2
.
In a standard CMOS process, a low-density implant step is performed by using a polysilicon gate as a mask to form what will later become lightly-doped drain (“L
DD
”) regions in the device substrate. An oxide layer is then formed over the device substrate and surrounds the gate. The oxide layer is etched, leaving oxide layers contiguous with the sides of the gate. These oxide layers are known as oxide spacers. Because the lateral dimensions of the spacers are usually very small, subsequent formation of suicides may bridge the separation between source and drain silicides and cause the gate to become short-circuited. This is known as salicide bridging.
The conventional method continues by forming raised source and drain regions. This may be accomplished through either epitaxial growth of silicon or deposition of silicon. Epitaxial growth requires high temperature that may cause excessive diffusion of impurities implanted to form the L
DD
regions. The step of depositing silicon to form raised source and drain regions may be accomplished through sputtering of silicon. A conventional sputtering process bombards a silicon target, or a sheet of pure silicon, with energetic ions to dislodge a plurality of silicon atoms from the target. Because the dislodged silicon atoms move in arbitrary directions, the silicon atoms will coat the entire surfaces of the spacers with silicon, which would require additional steps to remove the silicon from the undesired surfaces of the spacers. However, the silicon removal steps will damage the spacers, which would require additional steps to reform the spacers.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of forming raised source and drain regions that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures and methods particularly pointed out in the written description and claims thereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided a method for forming self-aligned silicide contacts on a semiconductor wafer having a gate dielectric layer and at least one polysilicon gate disposed over the gate dielectric layer. The method includes the steps of depositing a layer of spacer dielectric over the gate and the gate dielectric layer, masking the layer of spacer dielectric to define a source region and a drain region, while leaving the polysilicon gate exposed and anisotropically etching to remove the spacer dielectric deposited over the gate and the spacer dielectric and the gate dielectric layer disposed over the source region and the drain region to form sidewall spacers of the spacer dielectric contiguous with the gate. The method also includes the steps of collimated sputtering to deposit a layer of silicon, depositing a layer of metal and heating the wafer to induce silicide reaction between the deposited silicon and the deposited metal to form silicides over the source and drain regions and the gate.
In one aspect of the invention, the method also includes a step of removing the silicon layer deposited over the sidewall spacers.
In another aspect, the method includes a step of reforming the sidewall spacers.
Also in accordance with the invention, there is provided a method for forming raised source and drain regions on a semiconductor wafer that includes a gate dielectric layer and at least one polysilicon gate disposed over the gate dielectric layer. The method includes the steps of depositing a layer of spacer dielectric over the gate and the gate dielectric layer, masking the layer of spacer dielectric to define a source region and a drain region and leaving the polysilicon gate exposed, and anisotropically etching to remove the spacer dielectric deposited over the gate and the spacer dielectric and the gate dielectric layer disposed over the source region and the drain region to form sidewall spacers of the spacer dielectric contiguous with the gate. The method also includes the steps of collimated sputtering to deposit a layer of silicon, and implanting ions into the semiconductor wafer through the deposited layer of silicon to form source and drain regions in the wafer.
In one aspect of the invention, the method also includes the steps of depositing a layer of metal after the step of collimated sputtering, and heating the wafer to induce silicide reaction between the deposited silicon and the deposited metal.
In another aspect, the method additionally includes a step, prior to the step of depositing a layer of spacer dielectric, of implanting ions to form L
DD
regions.
Further in accordance with the invention, there is provided a method for forming a semiconductor device that includes the steps of defining a substrate, growing a first layer of dielectric material over the substrate, depositing a layer of polysilicon over the first layer of dielectric material, and patterning the layer of polysilicon and forming at least one gate. The method also includes the steps of depositing a second layer of dielectric material over the gate and the first dielectric layer, masking the second dielectric layer to define a source region and a drain region and leaving the gate exposed, and anisotropically etching to remove the second dielectric layer deposited over the gate and the first dielectric layer and the second dielectric layer disposed over the source region and the drain region to form sidewall spacers of the second dielectric contiguous with the gate. Additionally, the method includes the steps of collimated sputtering to deposit a layer of silicon, and implanting ions into the defined source and drain regions in the substrate through the deposited silicon.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5384281 (1995-01-01), Kenney et al.
patent: 5565383 (1996-10-01), Sakai
patent: 5656537 (1997-08-01), Iwamatsu et al.
patent: 5824586 (1998-10-01), Wollesen et al.

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