Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding
Reexamination Certificate
2007-01-16
2007-01-16
Barnie, Rexford (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Decoding
C326S038000, C326S040000, C326S041000, C326S047000, C326S102000, C257S302000, C257S314000, C257S315000
Reexamination Certificate
active
10929831
ABSTRACT:
One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and a second logic plane, each including a plurality of logic cells interconnected to implement a logical function. Forming the logic cells includes forming a horizontal substrate with a source region, a drain region, and a depletion mode channel region separating the source and the drain regions, and further includes forming a number of vertical gates located above different portions of the depletion mode channel region. At least one vertical gate is separated from the depletion mode channel region by a first oxide thickness, and at least one of the vertical gates is separated from the depletion mode channel region by a second oxide thickness. Other aspects and embodiments are provided herein.
REFERENCES:
patent: 4622648 (1986-11-01), Whitaker
patent: 4864375 (1989-09-01), Teng et al.
patent: 4896293 (1990-01-01), McElroy
patent: 4926224 (1990-05-01), Redwine
patent: 5006909 (1991-04-01), Kosa
patent: 5010386 (1991-04-01), Groover, III
patent: 5460988 (1995-10-01), Hong
patent: 5495441 (1996-02-01), Hong
patent: 5661055 (1997-08-01), Hsu et al.
patent: 5691230 (1997-11-01), Forbes
patent: 5696008 (1997-12-01), Tamaki et al.
patent: 5847425 (1998-12-01), Yuan et al.
patent: 5874760 (1999-02-01), Burns, Jr. et al.
patent: 5936274 (1999-08-01), Forbes et al.
patent: 5952039 (1999-09-01), Hong
patent: 5973352 (1999-10-01), Noble
patent: 5973356 (1999-10-01), Noble et al.
patent: 5991225 (1999-11-01), Forbes et al.
patent: 6034389 (2000-03-01), Burns et al.
patent: 6072209 (2000-06-01), Noble et al.
patent: 6083793 (2000-07-01), Wu
patent: 6114725 (2000-09-01), Furukawa et al.
patent: 6124729 (2000-09-01), Noble et al.
patent: 6134175 (2000-10-01), Forbes et al.
patent: 6143636 (2000-11-01), Forbes et al.
patent: 6150687 (2000-11-01), Noble et al.
patent: 6153468 (2000-11-01), Forbes et al.
patent: 6174784 (2001-01-01), Forbes
patent: 6184549 (2001-02-01), Furukawa et al.
patent: 6208164 (2001-03-01), Noble et al.
patent: 6219299 (2001-04-01), Forbes et al.
patent: 6222788 (2001-04-01), Forbes et al.
patent: 6238976 (2001-05-01), Noble et al.
patent: 6252267 (2001-06-01), Noble, Jr.
patent: 6281054 (2001-08-01), Yeo
patent: 6377070 (2002-04-01), Forbes
patent: 6403494 (2002-06-01), Chu et al.
patent: 6420902 (2002-07-01), Forbes et al.
patent: 6424001 (2002-07-01), Forbes et al.
patent: 6437389 (2002-08-01), Forbes et al.
patent: 6744082 (2004-06-01), Forbes et al.
patent: 2002/0109138 (2002-08-01), Forbes
Hergenrother, J. M., “The Vertical Replacement-Gate (VRG) MOSFET: A 50nm Vertical MOSFET with Lithography-Independent Gate Length”,IEEE, (1999),pp. 75-78.
Kalavade, Pranav, et al., “A novel sub-10 nm transistor”,58th DRC. Device Research Conference. Conference Digest, (Jun. 19-21, 2000),71-72.
Xuan, Peiqi , et al., “60nm Planarized Ultra-thin Body Solid Phase Epitaxy MOSFETs”,IEEE Device Research Conference, Conference Digest. 58th DRC. (Jun. 19-21, 2000),67-68.
Ahn Kie Y.
Forbes Leonard
Barnie Rexford
Schwegman Lundberg Woessner & Kluth P.A.
White Dylan
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