Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-10-10
2002-10-22
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S585000, C438S530000, C438S532000
Reexamination Certificate
active
06468888
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor fabrication, and more particularly to methods for fabricating improved ultra-large scale integration (ULSI) semiconductor devices such as ULSI metal oxide silicon field effect transistors (MOSFETs).
BACKGROUND OF THE INVENTION
Semiconductor chips or wafers are used in many applications, including as processor chips for computers, and as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
A common circuit component of semiconductor chips is the transistor. In ULSI semiconductor chips, a transistor is established by forming a polysilicon gate on a silicon substrate, and then forming a source region and a drain region side by side in the substrate beneath the gate by implanting appropriate dopant materials into the areas of the substrate that are to become the source and drain regions. The gate is insulated from the source and drain regions by a thin gate oxide layer, with small portions of the source and drain regions, referred to as “extensions”, extending toward and virtually under the gate. This generally-described structure cooperates to function as a transistor.
As discussed above, conventional transistor gates are made of polysilicon. As recognized herein, adding germanium to the polysilicon to render a transistor gate composition having the pseudo-chemical formula poly-Si
1−x
Ge
x
results in certain advantages over conventional polysilicon gates. One advantage is that a transistor with a poly-Si
1−x
Ge
x
gate structure has a “variable work function”. Stated differently, the threshold voltage of the transistor (a critical transistor performance characteristic) can be established by appropriately establishing the mole fraction of the germanium in the gate. This is a better way to establish a desired threshold voltage than by adjusting the dopant concentration in the channel region (i.e., the region between the source and drain under the gate), as currently must be done in polysilicon gate devices, because adjusting the dopant concentration in channel regions can cause unwanted short-channel effect and degradation of channel carrier mobility. Both short-channel effect and degradation of channel carrier mobility degrade the performance of the transistor.
Furthermore, when germanium is used in a polysilicon transistor gate, the dopant can be activated using lower activation temperatures during fabrication. Looked at another way, at a given temperature more dopant per unit time can be activated in poly-Si
1−x
Ge
x
. gate material than in polysilicon gate material. Consequently, two phenomena that degrade transistor performance—gate sheet resistance and gate depletion effect—are reduced in poly-Si
1−x
Ge
x
gates vis-a-vis polysilicon gates. Moreover, in general it is desirable to use relatively low temperatures, including low dopant activation temperatures, during semiconductor fabrication to reduce process cost and complexity and to reduce the risk of temperature-induced damage to chip components.
With the above in mind, the present invention recognizes the desirability of incorporating germanium into polysilicon transistor gates. However, the present invention further recognizes that a relatively high dose of germanium in the polysilicon must be implanted to achieve the above-mentioned advantages. Indeed, germanium doses in the range of 8×10
16
germanium atoms per square centimeter to 1×10
17
germanium atoms per square centimeter are required. As understood by the present invention, to achieve such high germanium doses, the implantation of germanium into the gate requires many hours, thereby prolonging fabrication time and correspondingly reducing production throughput. Fortunately, the present invention addresses the problem of achieving high germanium doses in polysilicon transistor gates while minimizing fabrication time and, thus, improving production throughput.
BRIEF SUMMARY OF THE INVENTION
A method is disclosed for establishing MOSFETs on a semiconductor device by forming a gate polysilicon layer on a semiconductor substrate, and then implanting germanium into the gate polysilicon layer. After implanting the germanium, the germanium is concentrated in a gate region of the gate polysilicon layer. In the preferred embodiment, the germanium is implanted into the gate polysilicon layer at a relatively low dose, preferably no more than 7×10
16
germanium atoms per square centimeter and more preferably no more than 1.6×10
16
germanium atoms per square centimeter.
Preferably, the concentrating step is undertaken by oxidizing a sacrificial region of the gate polysilicon layer to cause germanium in the sacrificial region to move into the gate region under the effect of interface dopant segregation. The germanium ion is repelled by the oxidized polysilicon sacrificial region, thus more germanium ions move into the gate region. Further, the sacrificial region is removed after the concentrating step, and an undoped polysilicon film deposited on the gate region. The polysilicon film and gate region are then patterned to establish one or more transistor gates on the substrate. A semiconductor device made according to the present method, and a digital processing apparatus incorporating the device, are also disclosed.
In another aspect, a method for making a semiconductor device includes forming at least one gate on a semiconductor substrate. The gate includes a gate insulating layer facing the substrate, and a polysilicon-germanium gate region on the gate insulating layer. Also, the gate includes a polysilicon layer on the gate region, with the polysilicon layer being substantially free of germanium.
In still another aspect, a semiconductor device includes a semiconductor substrate and one or more gate insulating layers on the substrate. One or more transistor gates are on the gate insulating layer. In accordance with the present invention, each gate includes a polysilicon-germanium gate region next to the gate insulating layer and an undoped polysilicon film on the polysilicon-germanium gate region.
Other features of the present invention are disclosed or apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION”.
REFERENCES:
patent: 5141895 (1992-08-01), Pfiester et al.
patent: 5633177 (1997-05-01), Anjum
patent: 6030874 (2000-02-01), Grider et al.
patent: 6252283 (2001-06-01), Gardner et al.
patent: 6262456 (2001-07-01), Yu et al.
patent: 2002/0005581 (2002-01-01), Kurata
Advanced Micro Devices , Inc.
Jr. Carl Whitehead
LaRiviere Grubman & Payne, LLP
Thomas Toniae M
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