Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
2002-08-22
2004-10-05
Nguyen, Van Thu (Department: 2824)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S778000
Reexamination Certificate
active
06800567
ABSTRACT:
TECHNICAL FIELD
Methods for fabricating highly integrated semiconductor devices are disclosed and, more particularly, methods for forming polyatomic layers of a semiconductor device are disclosed.
DESCRIPTION OF THE RELATED ART
Generally, as semiconductor devices become highly integrated and miniaturized, the area occupied by the constitutional elements gets smaller. Although as the size of a semiconductor device shrinks, however, a minimum capacitance should be secured to drive the device.
When fabricating a capacitor of a 64 Mbyte or 256 Mbyte-DRAM using a conventional dielectric material such as SiO
2
or Si
3
N
4
, the area occupied by the capacitor should be more than six times larger than the cell area to secure the essential capacitance, even though the SiO
2
or Si
3
N
4
layer is made as thin as possible. As a planar capacitor cannot fulfill this condition, a method for increasing the charge storage area is sought.
Many structures including a stack capacitor, a trench capacitor, or a hemispheric polysilicon layer have been suggested to increase the charge storage area or, in other words, to increase the storage node surface area of a capacitor. However, in case the structure of a capacitor is made complicated just to increase its charge storage area, there are problems that the production cost goes up and that the efficiency declines due to the complex manufacturing process.
Therefore, it is hard to apply a method of increasing the charge storage area of a capacitor by forming it in three-dimensional and fulfilling capacitance to a DRAM device over a 1 Gb class.
To solve these problems, studies have been conducted on the Ta
2
O
5
dielectric layer so as to substitute the conventional SiO
2
/Si
3
N
4
dielectric layer, but the capacitance of the Ta
2
O
5
layer is no more than two to three times that of the SiO
2
/Si
3
N
4
dielectric layer. Accordingly, to employ a Ta
2
O
5
dielectric layer to a highly integrated DRAM, the thickness of the dielectric layer must be reduced. But, this Ta
2
O
5
dielectric layer creates a problem as the amount of leakage current increases.
For this reason, a high dielectric thin film is needed to fabricate a capacitor for 1 Gb DRAMs. When using a thin film with a high dielectric constant, it's possible to obtain adequate capacitance only by a planar capacitor, thus simplifying the manufacturing process.
A(Ba,Sr)TiO
3
(hereinafter referred as BST) layer has been studied a lot as a high dielectric material. The capacitor adopting the BST layer has a capacitance dozens of times as big as that of adopting the SiO
2
/Si
3
N
4
group as well as the structure and thermal stability of the capacitor adopting SrTiO
3
and the excellent electric property of the capacitor adopting BaTiO
3
, which makes it an appropriate material for a memory device of over a 1 Gb class.
Among other materials having high dielectric constants, the BST layer of a perovskite structure is appropriately applicable to a high-density and high-integrated capacitor, which requires a high dielectric constant and small leakage current. This is because the BST layer features a high dielectric constant and superb insulation property with low dielectric dispersion and dielectric loss at a high frequency, and existing in a paraelectric at a room temperature. Furthermore, the BST layer doesn't have the problem of fatigue or degradation.
A polyatomic layer is formed with a sputtering deposition method, a chemical vapor deposition(CVD) method or an atomic layer deposition(ALD) method.
For forming a layer with the sputtering method, a high voltage is supplied to a target and inactive gases are injected to a vacuum chamber in order to generate plasma. For example, if an Ar gas is injected as the inactive gas, Ar ions are generated. The Ar ions are sputtered to the surface of the target and atoms are parted from the surface of the target. By this sputtering method, a thin film having high purity and good adhesion to a substrate may be deposited. However, in case of forming the multitudinous thin film composed of various atoms with the sputtering method, it is not easy to obtain the uniformity of the thin film, because the various atoms need the different optimum condition for depositing. Therefore, the sputtering method has limitations to be applied to form fine patterns.
The CVD is most widely used deposition method, a reaction gas and a source gas are used to form a thin film on a substrate to a required thickness. That is, various gases are injected to a reaction chamber, the gases excited by heat, light or plasma, chemically react each other, and the thin film is formed. In the CVD method, the deposition rate may be increased by controlling the deposition conditions, such as the plasma, chamber temperature and the ratio of reaction and source gases. However, it is difficult to control thermal stability of the atoms because of the rapid gas reaction and the physical and chemical properties of the thin film are deteriorated.
In the ALD method, a reaction gas and a purge gas are supplied alternately to form an atomic layer. The atomic layer formed with the ALD method shows good step coverage even if the atomic layer is formed on a structure having high aspect ratio, and it is possible to obtain a uniform layer at low pressure condition and to improve the electrical characteristic of the layer.
Lately, as the integration of the semiconductor device increases, the capacitor is formed with structures such as cylinder, fin, and stack structure, or is formed with a hemi spherical polysilicon layer in order to store much more charges in a small area. That is, the structure of charge storage electrodes of capacitors become complicated, therefore dielectric layers is formed with deposition methods, such as the ALD method, capable of guaranteeing good step coverage.
The ALD method use chemical reactions like as the CVD method, however the ALD method is distinguished from the CVD method in that the reaction gases are injected to a reaction chamber one by one without mixing between the reaction gases. For example, a gas A and a gas B are used as the reaction gases, firstly, the A gas is injected, and molecules of injected gas A are absorbed chemically on a substrate. Thereafter, inactive gases, such as Ar and N
2
are injected to the reaction chamber in order to purge the gas A remaining in the reaction chamber, and the gas B is injected to the reaction chamber. The injected gas B reacts with the molecules of the gas A only on the substrate, and an atomic layer is formed on the substrate. And then, the remaining gas B and accessory products are purged. The thickness of a layer is controlled by the repetition of the above-mentioned processes. Namely, the thickness of a layer formed by the ALD method closely relates to the number of repetition time.
Generally, the BST layer or STO layer is formed by the CVD method among above mentioned various deposition methods, and it is known that the BST layer has a best dielectric characteristics when the atomic ratio of Ba:Sr:Ti in the BST layer equals to 25:25:50. Therefore, in case of using the CVD method for forming the BST layer, for the purpose of obtaining intrinsic dielectric and excellent leakage current characteristics, it is needed to develop precursors and optimize the deposition condition in order to get the atomic ratio of Ba+Sr:Ti in the BST layer equal to 1:1. Hereinafter, Ba+Sr denotes a sum of atomic ratios of Ba and Sr.
FIG. 1
shows atomic ratio Sr/Ti dependency on step coverage, when a STO layer is formed in a three dimensional contact whose critical dimension CD is 0.15 &mgr;m. In
FIG. 1
, atomic ratio Sr/Ti dependencies of two STO layers are shown, that is, one STO layer is formed by flowing Sr source at a rate of 0.03 ml/min and Ti source at a rate of 0.1 ml/min (denoted to Sr:Ti=0.03:0.1 ml/min), and the other STO layer is formed by flowing Sr source at a rate of 0.045 ml/min and Ti source at a rate of 0.15 ml/min (denoted to Sr:Ti=0.034:0.15 ml/min). The two STO layers are formed with Sr(THD)
2
-pm
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
Nguyen Van Thu
Owens Beth E.
LandOfFree
Method for forming polyatomic layers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming polyatomic layers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming polyatomic layers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3308689