Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-29
2001-11-06
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S592000
Reexamination Certificate
active
06312999
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming an LDD structure with minimal lateral dopant diffusion in the fabrication of integrated circuits.
2. Description of the Prior Art
As the physical geometry of semiconductor devices shrinks, the channel length of the transistor is reduced as well. This leads to serious short channel effects. Since boron has a high diffusivity in the silicon substrate, lateral dopant diffusion is quite prominent when boron is used as the dopant for a PLDD structure. This lateral dopant diffusion will affect the threshold voltage and transistor current drive, thus affecting the device performance. In the traditional process flow, PLDD implantation is performed prior to source/drain implantation and annealing. The annealing process will enhance boron diffusion from the PLDD area into the channel underlying the gate electrode, causing the problems mentioned above.
U.S. Pat. No. 5,969,398 to Murakami teaches plasma doping of the gate and source/drain regions. U.S. Pat. Nos. 5,866,460 and 5,998,274, both to Akram et al teach a method to form source and drain subregions each having a different dopant concentration in a polycide process. U.S. Pat. No. 5,913,112 to Yamazaki et al discloses formation of LDD regions after the gate has been oxidized. The oxidized portion of the gate acts as a mask for the LDD implantation.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of forming a MOSFET having an LDD structure.
A further object of the invention is to provide a method of forming a MOSFET having an LDD structure with minimal lateral dopant diffusion.
Yet another object is to provide a method of forming a MOSFET having a PLDD structure with minimal lateral dopant diffusion.
Yet another object is to provide a method of forming a MOSFET having a PLDD structure with minimal lateral boron dopant diffusion.
A still further object of the invention is to provide a method of forming a MOSFET having an LDD structure with minimal lateral dopant diffusion wherein the LDD structure is formed after S/D implantation and annealing.
Another still further object of the invention is to provide a method of forming a MOSFET having an LDD structure with minimal lateral dopant diffusion wherein the LDD structure is formed after S/D implantation, annealing, and silicidation.
Yet another object of the invention is to provide a method of forming a MOSFET having an LDD structure with minimal lateral dopant diffusion wherein the LDD structure is formed by plasma doping after S/D implantation, annealing, and silicidation.
In accordance with the objects of this invention a method for forming a MOSFET having an LDD structure with minimal lateral dopant diffusion is achieved. A gate electrode is provided overlying a gate dielectric layer on a semiconductor substrate. Dielectric spacers are formed on sidewalls of the gate electrode. Source and drain regions are formed associated with the gate electrode. The gate electrode and source and drain regions are silicided. Thereafter, the spacers are removed to expose the semiconductor substrate. LDD regions are formed by plasma doping in the exposed semiconductor substrate between the source and drain regions and the gate electrode to complete formation of an LDD structure in the fabrication of an integrated circuit device.
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patent: 5913112 (1999-06-01), Yamazaki et al.
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Balasubramaniam Palanivel
Chivukula Subrahamanyam
Mukhopdhyay Madhusudan
Pradeep Yelehanka Ramachandramurthy
Chartered Semiconductor Manufacturing Ltd.
Lebentritt Michael
Pike Rosemary L. S.
Saile George O.
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