Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure
Reexamination Certificate
2000-12-18
2002-05-21
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
Having specified scribe region structure
C438S401000, C438S633000, C438S975000, C257S797000
Reexamination Certificate
active
06391745
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming overlay alignment structures, such as an overlay vernier, for semiconductor devices and, in particular, to an improved method for forming an overlay alignment structure that prevents deformation of the alignment target or mother vernier.
2. Description of the Background Art
During the production of semiconductor devices having a stacked structure, photolithography processes are commonly used to produce various functional device structures. Because the relative position of structures formed from sequential layers is critical to the performance of the resulting semiconductor devices, alignment structures, such as overlay verniers, are typically formed during each photolithography process in order to observe, evaluate and possibly correct misalignment between a previously-formed layer and a current layer. An overlay vernier typically consists of a mother vernier that was formed in a previous process, and a corresponding son vernier that is formed during the current process. The overlay vernier is generally formed on a scribe line of a wafer. Typically, the mother vernier comprises a structure formed during a previous etch process on a layer underlying the current layer and the corresponding son vernier is formed from a portion of the photoresist pattern for the current layer.
FIG. 1A
is a cross-sectional view illustrating the mother vernier formed in a second polysilicon layer (poly
2
) layer, and
FIG. 1B
is a plan view illustrating the mother vernier.
Referring to
FIGS. 1A and 1B
, the mother vernier
3
is formed when the poly
2
layer, i.e., the bit line pattern, is being formed in the cell regions. In this illustration, the mother vernier
3
is formed in a box shape, and has in its center portion an alignment space for the son vernier that will be formed in a subsequent process. In addition, the mother vernier
3
, like the poly
2
pattern, is formed on an interlayer insulating film
2
that is intended to prevent electrical contact between the gate electrode and the bit line. One material that has proven suitable for forming the interlayer insulating film
2
is a plasma enhanced tetraethylorthosilicate (PE-TEOS).
As shown in
FIG. 1A
, a flowable insulating film
1
, for example a BPSG film, is commonly used to planarize the surface of the substrate after a first set of polysilicon structures have been formed from the polyl layer (not shown). The PE-TEOS film
2
is formed on the BPSG film
1
, and the mother vernier
3
is, in turn, formed on the PE-TEOS film
2
.
However, the conventional mother vernier is formed on the flowable insulating film, and thus may be deformed due to shrinkage or other movement of the flowable insulating film during subsequent thermal processes. As a result, when a deformed mother vernier is used as the alignment target for forming an overlay vernier with a subsequent son vernier, the accuracy of the alignment between the upper and lower layers is decreased, thereby increasing the potential for producing shorts during subsequent metal interconnection processes.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a method for forming an overlay vernier that can prevent the mother vernier from being deformed.
In order to achieve the above-described object of the present invention, there is provided a method for forming an overlay vernier, comprising the steps of: forming a planarization film on a wafer where a predetermined basic substructure has been formed; etching the planarization film to expose a predetermined region of a scribe line of the wafer where the overlay vernier will be formed; depositing a first polysilicon layer on the planarization film and the exposed wafer region; polishing the first polysilicon layer until the surface of the planarization film is exposed; forming an interlayer insulating film on the planarization film and the remained first polysilicon layer; etching the interlayer insulating film to expose a region of the first polysilicon layer where the mother vernier of the overlay vernier will be formed; depositing a second polysilicon layer on the interlayer insulating film and the exposed first polysilicon layer; and patterning the second polysilicon layer to form the mother vernier.
REFERENCES:
patent: 5503962 (1996-04-01), Caldwell
patent: 5898227 (1999-04-01), Geffken et al.
patent: 5919714 (1999-07-01), Chen et al.
patent: 5935764 (1999-08-01), Kakehashi
patent: 6133111 (2000-10-01), Sur et al.
patent: 6316328 (2001-11-01), Komuro
patent: 2001-203159 (2001-07-01), None
Hynix / Semiconductor Inc.
Jr. Carl Whitehead
Vockrodt Jeff
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