Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-12-18
2003-02-18
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S316000
Reexamination Certificate
active
06521499
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a non-volatile memory, and more particularly to a method for forming a non-volatile memory with a self-aligned contact.
2. Description of the Related Art
Very large scale integration (VLSI) and more recently, the ultra scale integration (ULSI) of integrated circuits require semiconductor contact structures that provide high levels of performance. It is well known that in the progression of integrated circuits, as device dimensions approached the sub-micron regime, the conventional contacts used up to that point began to limit device performance in several ways. It was not possible to minimize the contact resistance when the contact hole was also scaled down for the contact resistance went up inversely with the smaller contact area. In addition, the area of the diffusion regions could not be minimized because the contact hole had to be aligned to these regions with a separate masking step, and extra regions had to be allocated for misalignment. The larger regions also resulted in increased junction capacitance between diffusion region and substrate, which slowed down the device speed. As a result, methods had to be developed to reduce the contact areas commensurate with the large-scale integration technology.
In view of the drawbacks mentioned with the prior art process, there is a continued need to develop new and improved processes that overcome the disadvantages associated with prior art processes. The advantages of this invention are that it solves the problems mentioned above.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method for forming a non-volatile memory with an upgraded process window.
It is another object of this invention to provide a new non-volatile memory structure that can prevent any process issues and device failures resulting from the etching of the contact holes.
It is a further object of this invention to provide a novel method for forming a reliable non-volatile memory structure.
To achieve these objects, and in accordance with the purpose of the invention, the invention uses elevated buried diffusion polysilicon layers (BDPOLY) and spacers to form contacts so that the process window can be upgraded. The spacers can be used as an etching stop layer so that the misalignment of contact holes will not present any process issues and device failures resulting from the following etching of the contact holes. The invention uses a method comprising the following steps. First of all, a substrate having a first dielectric layer thereon, a first conductive layer on said first dielectric layer and a second dielectric layer on said first conductive layer is provided. Then a pattern of buried diffusion regions is transferred into said second dielectric layer and said first conductive layer to expose said first dielectric layer and form a plurality of conductive lines. Next a third dielectric layer is formed over said substrate. Furthermore, said third dielectric layer is etched back to expose said substrate and said second dielectric layer and form spacers adjacent the side walls of said conductive lines. Moreover, an ion implantation process is performed on said substrate to form the buried diffusion regions in said substrate. Then a second conductive layer is formed over said substrate. Next said second conductive layer is etched back to a level lower than the top of said spacers. Moreover, the top surface of said second conductive layer is oxidized to form an oxide layer. Said second dielectric layer is then removed. Furthermore, a third conductive layer is formed over said substrate. Next a fourth conductive layer is formed over said third conductive layer. Then a fourth dielectric layer is formed over said fourth conductive layer. Next a word line pattern comprising a plurality of word line substantially perpendicular to said conductive lines is transferred into said fourth dielectric layer, said fourth conductive layer and said third conductive layer to expose said oxide layer. Furthermore, a fifth dielectric layer is formed over said substrate. Moreover, a sixth dielectric layer formed over said fifth dielectric layer. Then said sixth dielectric layer is etched back to expose said fifth dielectric layer. Next a seventh dielectric layer is formed over said substrate. Finally, contact holes are formed into said seventh dielectric layer and said oxide layer to expose said conductive lines.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 5741719 (1998-04-01), Kim
patent: 6440803 (2002-08-01), Huang et al.
Hwang Quoc
Macronix International Co. Ltd.
Nelms David
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