Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-10
2002-04-23
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S266000
Reexamination Certificate
active
06376306
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an improved method of making non-volatile memory structures in a semiconductor substrate, and, more specifically to an improved method of making memory structures that comprises different steps than those previously used.
2. Description of Related Art
Embodiments of the invention relate, in particular but not exclusively, to a method of fabricating non-volatile memory structures, and reference will be made to this field of application in the ensuing description for convenience of explanation.
As is well known, non-volatile memory structures comprise a memory matrix constructed from non-volatile memory cells, each comprising a floating gate MOS transistor and associated selection transistor, and control circuitry which comprises active elements, such as MOS transistors.
According to the prior art some of the transistors provided in the memory structure may have source and drain regions formed by an LDD (Lightly Doped Drain) deposition technique. A process flow for making such memory structures is illustrated by
FIGS. 1 and 2
, wherein the memory structures are denoted by the reference numeral
100
.
The memory structure
100
comprises a memory matrix
30
, and circuitry
90
associated with the matrix
30
. The structure
100
is integrated in a semiconductor substrate
20
, and the process flow for its fabrication includes forming initially a layer
150
of field oxide on the substrate
20
surface. This field oxide layer
150
is then removed selectively to produce the active areas wherein the non-volatile memory cells
40
of the matrix
30
are later formed.
A stacked structure, comprising a first polysilicon layer
170
, an intermediate dielectric layer
180
, a second polysilicon layer
190
, and a transition metal layer
200
, is subsequently deposited onto the substrate portion which is to accommodate the matrix
30
. Using a conventional photolithographic technique, the stacked structure is defined with gate electrodes
70
of the cells
40
, in the active areas of the matrix
30
.
Simultaneously therewith, gate electrodes
80
of the selection transistors of the memory cells
40
are optionally defined in the field oxide layer
150
of the matrix
30
.
The circuitry
90
of the matrix
30
is instead deposited a stacked structure, comprising the second polysilicon layer
190
and the transition metal layer
200
, in which structure gate electrodes
110
for transistors
101
in the circuitry
90
are defined.
The process flow is continued conventionally until the entire surface of the substrate
20
is deposited a dielectric layer
120
, later to be used for defining isolation spacers.
In the prior art, isolation side spacers
140
, adjoining each gate electrode
70
,
80
of the cell
30
and the selection transistors, are defined at the same time as isolation side spacers
130
are defined which adjoin each gate electrode
110
of the transistors in the circuitry
90
. However, in etching away the dielectric layer
120
in order to form the isolation spacers
130
,
140
, the etching will also affect the field oxide layer
150
of the matrix
30
. Thus, openings
141
and
131
are created in this oxide layer
150
.
The presence of such openings
141
and
131
may result in increased junction leakage current. This effect is intensified by using the differential field process flow whereby the thickness is smaller at the matrix than at the circuitry.
The process flow is continued conventionally with the use of a resist mask, known as mask
605
in the process flow employed by the Applicant, following a semiconductor annealing step. This mask is used for defining heavily doped regions with a first type of conductivity of the transistors
101
in the circuitry
90
.
By a first implantation using arsenic ions, the heavily doped regions with a first type of conductivity of the transistors
101
in the circuitry
90
can be defined.
After removing the mask
605
, a second mask—known as mask
655
in the process flow employed by the Applicant—is used to define heavily doped regions with a second type of conductivity of the remaining transistors
101
in the circuitry
90
.
By a second implantation using, preferably, boron ions, the heavily doped regions with a second type of conductivity of the remaining transistors
101
in the circuitry
90
can be defined.
SUMMARY OF THE INVENTION
Embodiments of this invention provide an improved method of making memory structures, whereby the shortcomings connected with defining the isolation spacers that beset prior art memory structures can be removed.
Embodiments of the present invention have the memory matrix screened off during the step of etching away the oxide layer to define isolation spacers for the circuitry transistors by means of a mask already provided in standard processes.
Based on this principle, an embodiment of this invention provides for forming a screening layer over the whole surface of the memory structure; masking, using photolithographic methods, to define regions to be implanted for circuitry transistors; etching away the dielectric layer to define side isolation spacers adjoining each gate electrode of the circuitry transistors; and imparting, as by implantation, a predetermined conductivity to the implanted regions of the circuitry.
In some embodiments, a step of partially etching back the dielectric layer is carried out before forming the screening layer.
The features and advantages of a device according to the invention can be more clearly understood by reading the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.
REFERENCES:
patent: 5303185 (1994-04-01), Hazani
patent: 5768186 (1998-06-01), Ma
patent: 6211548 (2001-04-01), Ma
Camerlenghi Emilio
Colabella Elio
Iannucci Robert
Jorgenson Lisa K.
Nelms David
Nhu David
Seed IP Law Group PLLC
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