Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-02
2003-06-10
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S276000, C438S278000, C438S512000
Reexamination Certificate
active
06576511
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method for forming a memory, and more particularly to a method for a read only memory.
2. Description of the Prior Art
Recently, developments have included various techniques for increasing the density of integration of the semiconductor memory device and decreasing the voltage thereof. A memory is a semiconductor device used to store data or information, wherein the memory has a plurality of cells such as a plurality of memory units for storing the data or information. The memory cells are arranged within an array to connect with word line and bit line, so as to perform their function for reading or writing. There are two types of memory, one is random access memory (RAM) and another is read only memory (ROM). A random access memory is an array of latches, each with a unique address, having an addressing structure that is common for both reading and writing. Data stored in most types of RAM's is volatile because it is stored only as long as power is supplied to the RAM. A read only memory (ROM) is a circuit in which information is stored in a fixed, nonvolatile manner, that is, the stored information remains even when power is not supplied to the circuit.
By convention, the read only memories have various styles, which can be classed by different methods for storing information, such as a programmable read only memory (PROM) is one in which the information is stored after the device is fabricated and packaged, erasable programmable read only memories (EPROM) are programmable read only memory that can be completely erased and reprogrammed, electrically erasable programmable read only memories (EEPROM) and a mask read only memory (MROM). The mask read only memory is a device for programming a desired cell transistor by selectively implanting impurity ions into a channel region of the cell transistor in the course of fabricating the same. Once information is programmed, the information cannot be erased. Thus, it is a non-volatile memory.
A control gate and a floating gate have long been utilized for forming a memory. Electrons are moved onto or removed from the floating gate of a given memory cell in order to program or erase its state. The floating gate is surrounded by an electrically insulated dielectric. Since the floating gate is well insulated, this type of memory device is not volatile; that is, the floating gate retains its charge for an indefinite period without any power being applied to the device. Moreover, if enough electrons are so injected into the floating gate, the conductivity of the channel of the field effect transistor of which the floating gate is a part is changed. Hence, a control gate is coupled with the floating gate through a dielectric layer and acts as a word line to enable reading or writing of a single selected cell in a two-dimensional array of cells. One type of memory array integrated circuit chip includes elongated, spaced apart source and drain regions formed in a surface of a semiconductor substrate, wherein the source and drain regions form the bit lines of the memory. A two-dimensional array of floating gates has each floating gate positioned in a channel region between adjacent source and drain regions, while the control gate is positioned over each row of floating gates in a direction transverse to the source and drain regions, wherein the control gates are the word lines of the memory array.
If the read only memory has a structure, such as nitride layer, it is called nitride read only memory (NROM). There are two processes for fabricating the nitride read only memory (NROM) cells. In the first process, bit lines are first created in the substrate, after which the surface is oxidized. Following the oxidation, the ONO layers are added over the entire array. The word lines are then deposited with polysilicon in rows over the ONO layers. In the second process, the ONO layers are formed over the entire array first, on top of which conductive blocks of polysilicon are formed. The bit lines are implanted between the blocks of polysilicon after which the ONO layers are etched away from on top of the bit lines. Planarized oxide is then deposited between the polysilicon blocks after which polysilicon word lines are deposited.
FIG. 1
, to which reference is made, illustrates a typical prior art nitride read only memory cell. This nitride read only memory cell includes a substrate
100
in which are implanted a source
110
and a drain
120
and on top of which lies an oxide-nitride-oxide (ONO) structure
130
having a layer of nitride
150
sandwiched between two oxide layers
140
and
160
. On top of the ONO structure
130
lies a gate conductor
170
. Between source
110
and drain
120
is a channel
180
formed under ONO structure
130
. Nitride section
150
provides the charge retention mechanism for programming the memory cell. Specifically, when programming voltages are provided to source
110
, drain
120
and gate conductor
170
, electrons flow towards drain
120
. According to the hot electron injection phenomenon, some hot electrons penetrate through the lower section of silicon oxide
140
, especially if silicon oxide section
140
is thin, and are then collected in nitride section
150
.
As shown in
FIG. 1B
, which is known in the art, nitride section
150
retains the received charge in a concentrated area adjacent drain
120
. Concentrated charge
190
significantly raises the threshold voltage of the portion of the channel
180
of the memory cell under charge
190
to be higher than the threshold voltage of the remaining portion of the channel
180
. When concentrated charge
190
is present (that is, the cell is programmed), the raised threshold voltage of the cell does not permit the cell to be placed into a conductive state during reading of the cell. If the concentrated charge
190
is not present, the read voltage on gate conductor
170
can overcome the much lower threshold and, accordingly, channel
180
becomes inverted and hence, conductive. Nevertheless, it is necessary to provide a large of voltage for programming of conventional read only memory, so as to overcome difference of potential energy that is very high. Therefore, the process complexity is increased and, hence, cost is increased.
In accordance with the above description, a new and improved method for forming the nitride read only memory is therefore necessary, so as to raise the yield and quality of the follow-up process.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for fabricating the read only memory that substantially overcomes the drawbacks of the above mentioned problems which arise from the conventional methods.
Accordingly, it is a main object of the present invention to provide a method for fabricating the read only memory having a charge trapping dielectric sandwiched between two silicon dioxide layers. This invention can use exposure of high energy light for programming the memory, so as to accelerate sufficiently electrons at the high energy light irradiated region to inject into the region of the trapping dielectric layer. Hence, the present invention is appropriate for deep sub-micron technology to provide the semiconductor devices.
Another object of the present invention is to provide a method for forming the nitride read only memory. The present invention can define an array of memory cells to have binary threshold states. Furthermore, a non-high energy light-penetrable film is deposited and is patterned to define programming cell regions and non-programming cell regions for having binary threshold states. Hence, this invention can decrease differences of potential energy without higher voltage circuitry for electrical programming. Moreover, no program circuitry is required for nitride read only memory cell programming, so as to reduce process complexity and, hence, cost. Therefore, the present invention can provide positive economic effects.
In accordance with the present invention, a new method
Chen Chia-Hsing
Hsiung Minnie
Lin Chun-Jung
Pan Samuel
Macronix International Co. Ltd.
Nelms David
Nguyen Dao H.
Powell Goldstein Frazer & Murphy LLP
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