Method for forming multiple gate oxide layers

Details Method for forming multiple gate oxide layers Method for forming multiple gate oxide layers

2003-06-24

2004-05-11

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

C438S776000, C438S981000

Reexamination Certificate

active

06734113

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device; and, more particularly, to a method for forming multiple gate oxide layers.
DESCRIPTION OF RELATED ARTS
It has been recently researched on System On Chip (SOC) technology that enables various devices with different purposes to be formed in one chip in order to satisfy requirements and needs of diverse products. In such SOC technology, each device has a, different driving voltage and includes gate oxide layers having different thicknesses obtained by using different processes are formed. That is, a high voltage device supplied with a high voltage needs a thick oxide layer for improving reliability, and a low voltage device focusing on a driving speed of the device needs a thin oxide layer.
It is a dual gate oxide layer formation technology developed to meet the above demand.
Instead of using different processes to provide different thicknesses to two devices, gate oxide layers having different thicknesses are formed in a device divided into three different regions within one chip, thereby improving layout and margins of the device and manufacturing various products. For instance, it is possible to form each gate oxide layer into a high voltage device, a low voltage device and a medium voltage device based on its appropriate purpose.
Accordingly, it is required of such multiple gate oxide layer formation technology capable of varying a thickness of the gate oxide layer according to a particular purpose of a device.
A conventional multiple gate oxide technique is disclosed in U.S. Pat. No. 6,110,842 issued on Aug. 29, 2000.
FIGS. 1A
to
1
C are cross-sectional views showing a method for forming multiple gate oxide layers according to a prior art.
Referring to
FIG. 1A
, a resist pattern
12
exposing a partial portion
16
of a semiconductor substrate
10
is formed on the semiconductor substrate
10
. An oxynitride layer or a thin nitride layer
18
is formed on the exposed semiconductor substrate
10
by using a high-density plasma nitridation technique.
Referring to
FIG. 1B
, the resist pattern is then removed.
Referring to
FIG. 1C
, dual gate oxide gate layers of a thick silicon oxide layer
20
A and a thin silicon oxide layer
20
B are formed on the semiconductor substrate
10
through an oxidation process.
At this time, the nitride layer
18
formed on the partial portion
16
of the semiconductor substrate
10
delays the oxidation on the surface of the semiconductor substrate
10
so that the thinner silicon oxide layer
20
B is formed on the partial portion
16
. The thick oxide layer
20
A is formed on a surface
14
of the semiconductor substrate
10
without the nitride layer
18
.
In the above-described prior art, only the dual gate oxide layers are formed since the surface of the semiconductor substrate is selectively proceeded with the nitridation. There is also a disadvantage of complicating the process if this conventional technique is applied to form multiple gate oxide layers.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for forming multiple gate oxide layers capable of overcoming limitations in a dual gate oxide layer technology based on a conventional nitridation method and forming diverse devices including multiple gate oxide layers with different thicknesses in one chip by using a simple process.
In accordance with an aspect of the present invention, there is provided a method for forming multiple oxide layers, including the steps of: forming a first gate oxide layer on a semiconductor substrate; forming a first masking layer on the first gate oxide layer, the first masking layer covering a first region of the first gate oxide layer; performing nitridation to a surface of a second region of the first gate oxide layer exposed by the first masking layer; removing the first masking layer; forming a second masking layer covering the first and the second regions of the first gate oxide layer but exposing a partial portion of the second region, the partial portion is defined as a third region of the first gate oxide layer; exposing a surface of the semiconductor substrate by etching the third region of the first gate oxide layer exposed by the second masking layer; and forming a second gate oxide layer on the exposed semiconductor substrate and the first region of the first gate oxide layer.


REFERENCES:
patent: 5254489 (1993-10-01), Nakata
patent: 6110842 (2000-08-01), Okuno et al.
patent: 6261972 (2001-07-01), Tews et al.
patent: 6331492 (2001-12-01), Misium et al.

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