Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1998-05-07
2000-06-13
Utech, Benjamin L.
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438723, 438724, 438737, 438743, 438744, H01L 21306
Patent
active
060749520
ABSTRACT:
A method of forming a plurality of contact holes 70 in a semiconductor wafer uses a single step. The semiconductor wafer includes a dielectric layer 69 overlying a silicon substrate 51, a silicon nitride layer 67a, and a silicon oxynitride layer 63c. First, a photoresist 68 layer is developed on the dielectric layer. Prior to forming the dielectric layer, the silicon oxynitride layer is formed overlying a first conductive layer, and the silicon nitride layer is formed overlying a second conductive layer. Second, an etching step is performed to etch through the silicon oxynitride layer, the silicon nitride layer, a portion of the dielectric layer above the silicon oxynitride layer, and the silicon nitride layer to expose the silicon substrate 51, the first conductive layer 63a, and the second conductive layer 67c. The etching recipe includes a first chemistry and a second chemistry. The first chemistry includes C.sub.2 F.sub.6, C.sub.4 F.sub.8, CH.sub.3 F, and Ar. The second chemistry is chosen from a group including O.sub.2, CO.sub.2, CO and any combination thereof. Thus, a plurality of contact holes is formed above the silicon substrate, the first conductive layer and the second conductive layer.
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Chen Bi-Ling
Jeng Erik S.
Lien Wan-Yih
Liu Hao-Chieh
Champagne Donald L.
Utech Benjamin L.
Vanguard International Semiconductor Corporation
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