Method for forming multi-layered interconnect structure

Details Method for forming multi-layered interconnect structure Method for forming multi-layered interconnect structure

2001-02-15

2003-02-04

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S624000, C438S629000, C438S634000, C438S638000, C438S672000

Reexamination Certificate

active

06514856

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a multi-layered interconnect structure and a method for forming the same, especially to the multi-layered interconnect structure having a reduced connection resistance and smaller dimensions and the method for forming the same.
(b) Description of the Related Art
The development of the interconnect structure with smaller dimensions is necessary for achieving the higher integration in the semiconductor device. As a method for forming such an interconnect structure, a so-called dual-damascene technology which is developed by improving an embedded damascene technology attracts more and more attention.
In the dual-damascene technology, a multi-layered interconnect structure is formed including an underlying interconnect layer, an overlying interconnect layer and conductive via-plugs penetrating the interlayer dielectric film for connecting both the interconnect layers.
In the conventional damascene technology, as shown in
FIG. 1A
, after a dielectric film
14
such as a silicon dioxide (SiO
2
) film is formed overlying a semiconductor substrate
12
, an underlying interconnect
16
is formed in the trench of the dielectric film
14
by using the damascene technology. The underlying interconnect
16
includes a barrier metal layer
16
a
formed by a material such as TiN and a main interconnect
16
b
formed by a material such as Cu.
For forming the underlying interconnect
16
, at first, a photoresist film not shown in the drawings is formed on the dielectric film
14
. Then, after an etching mask having a trench pattern for interconnect trenches is formed by photolithographically patterning the photoresist film, the dielectric film
14
is etched by the anisotropic dry etching technology to form the interconnect trenches in the dielectric film
14
.
Next, the barrier metal layer
16
a
and then the main interconnect
16
b
are deposited on the dielectric film
14
and simultaneously fill the inner spaces of the interconnect trenches.
The underlying interconnect
16
embedded in the interconnect trench of the dielectric film
14
as shown in
FIG. 1A
is formed by removing the unnecessary Cu layer
16
b
and barrier metal layer
16
a
on the dielectric film
14
by using a CMP (chemical mechanical polishing) process.
Then, in order to prevent the outward diffusion of the Cu in the embedded underlying interconnect
16
, a SiN film
18
is formed overlying the entire surface of a wafer or on the dielectric film
14
and the underlying interconnect
16
as shown in FIG.
1
B.
Thereafter, a SiO
2
film
20
acting as an interlayer dielectric film, a SiON film
22
acting as an etch stop layer, and a SiO
2
film
24
acting as a dielectric film for filling an overlying interconnect are sequentially formed on the entire surface of the wafer.
Then, a photoresist film is formed on the SiO
2
film
24
to form an etching mask
26
having a pattern for a through-hole
28
in which the conductive via-plug is formed. Next, the SiO
2
film
24
, the SiON film
22
and the SiO
2
film
20
are etched by using the anisotropic dry etching technology to form the through-hole
28
which exposes the SiN film
18
as shown in FIG.
1
C. Then, after the removal of the etching mask
26
, as shown in
FIG. 1D
, another photoresist film is deposited on the entire wafer surface to form an etching mask
32
having a pattern of interconnect trenches for the overlying interconnect in communication with the through-hole
28
.
A part of the SiO
2
film
24
uncovered with the etching mask
32
is etched by using the anisotropic dry etching technology to form an interconnect trench
34
as shown in FIG.
1
E. The etching for forming the interconnect trench
34
is stopped by the SiON film
22
acting as the etch stop layer.
Then, as shown in
FIG. 1F
, the underlying interconnect
16
is exposed by the successive removals of the etching mask
32
, the exposed SiON film
22
and the SiN film
18
.
Next, a barrier metal layer
36
a
formed by a TiN film and a main interconnect layer
36
b
formed by Cu is formed on the entire wafer surface, thereby filling the through-hole
28
and the interconnect trench
34
.
The unnecessary barrier metal layer
36
a
and main interconnect layer
36
b
on the SiO
2
film
24
is removed by using the CMP process, thereby, as shown in
FIG. 1H
, forming a conductive via-plug
38
in the through-hole
28
and an overlying interconnect
36
in the interconnect trench
34
.
In this manner, the multi-layered interconnect structure including the underlying interconnect
16
and the overlying interconnect connected to the underlying interconnect
16
through intermediary of the conductive via-plug
38
can be formed by using the dual-damascene technology which includes a less number of steps than the damascene technology.
However, the conventional dual-damascene technology includes the following problems.
A first problem is that, as shown in
FIG. 2A
, the inner wall of the through-hole
56
formed in the preceding step is simultaneously etched when the interconnect trench
54
is formed, thereby increasing the diameter of the through-hole
56
. The increase of the diameter is a bar to the smaller dimensions and the higher integration of the interconnect structure.
A second problem is that, as shown in
FIG. 2A
, the SiN film
48
covering the underlying interconnect
46
is simultaneously etched, when the interconnect trench
54
is formed, to expose the underlying interconnect
46
. As a result, when the etching mask
52
used for forming the interconnect trench
54
is removed by using an O
2
-ashing process, the underlying interconnect
46
is simultaneously oxidized to increase the connection resistances of the conductive via-plug and the underlying interconnect
46
.
A third problem is that, as shown in
FIG. 2B
, the thickness of the photoresist film deposited for forming the etching mask
74
is reduced, during the formation of the interconnect trench
76
, in the region where the through-holes
78
are densely formed due to the influence of the concave shape of the through-holes
78
, thereby disabling the formation of the interconnect trench
76
having the precise dimensions.
JP-A-10(1998)-223755 describes a method for preventing the increase of the parasitic capacity of the overlying interconnect or the underlying interconnect, and the increase of the size of the through-hole by utilizing an organic film.
As shown in
FIG. 3A
illustrating another conventional dual-damascene technology recited in the above publication, after the formation of an underlying interconnect
44
overlying a substrate
42
, a first SiO
2
film
46
and a SiN film are sequentially deposited overlying the substrate
42
, and the SiN film is etched to form an etching mask
48
having a pattern for through-holes.
Then, as shown in
FIG. 3A
, after the successive formation of a second SiO
2
film
50
and an etching mask
52
formed by a photoresist film, the second SiO
2
film
50
is etched by using the etching mask
52
to form an interconnect trench
54
of an overlying interconnect. Further, the first SiO
2
film
46
is etched by using the etching mask
48
to form a through-hole
56
.
Next, though not shown in the drawings, after the removal of the etching mask
52
, a metal film is deposited to fill the through-hole
56
and the interconnect trench
54
, and the metal film on the second SiO
2
film
50
is removed by using the CMP technique, thereby forming a conductive via-plug having the filled through-hole
56
and an overlying interconnect having the filled interconnect trench
54
.
According to the technique described in the above publication, however, the SiN film used as the etching mask
48
and existing between the first SiO
2
film
46
and the second SiO
2
film
50
increases the parasitic capacity of the interconnect, and the periphery of the aperture of the etching mask
48
is also etched when the first SiO
2
film
46
is etched to enlarge the diameter of the through-hole
56
.
In accordance

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