Method for forming multi-layer wiring structure

Details Method for forming multi-layer wiring structure Method for forming multi-layer wiring structure

2006-02-07

2006-02-07

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S662000, C438S624000, C438S787000

Reexamination Certificate

active

06995096

ABSTRACT:
For suppressing decomposition of an organic group (for example, a CH3group) which is bonded to an Si atom of an organic SOG film for use in a flattening process at the time of an ashing process, there is provided a method comprising the steps of: forming an organic SOG layer directly on a lower wiring layer or on a predetermined film including a hillock protection layer which is formed on the lower wiring layer in advance; forming an upper wiring layer on the organic SOG layer without using an etching back process; forming a via hole through an etching process by using a patterned resist layer provided on the upper wiring layer as a mask; performing an ashing process with a plasma by making ions or radicals which are induced from oxygen gas as a main reactant, under an atmospheric pressure ranging from 0.01 Torr to 30.0 Torr; and filling said via hole with a conductive material so as to electrically connect the lower wiring layer to the upper wiring layer.

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