Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-10
2001-08-14
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C438S301000
Reexamination Certificate
active
06274444
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a MOS field effect transistor (MOSFET).
2. Description of the Related Art
An integrated circuit (IC) is composed of many devices and isolation structures that isolate the devices. The isolation structures, such as STI structure or field oxide isolation structure, are used to prevent carriers from moving between devices. Conventionally, the isolation structures are formed within a concentrated semiconductor circuit, for example, between adjacent field effect transistors (FET) in a dynamic random access memory (DRAM), to reduce a leakage current produced by the FET.
An isolation region is formed in an integrated circuit for preventing a short circuit from occurring between adjacent device regions on a substrate. Conventionally, a local oxidation of silicon (LOCOS) technique is widely utilized in the semiconductor industry to provide isolation regions on semiconductor device. However, since internal stress is generated and bird's beak encroachment occurs in the isolation structures, LOCOS cannot effectively isolate devices.
The shallow trench isolation (STI) technique has been developed to improve the bird's beak encroachment of the LOCOS so as to achieve an effective isolation structure. Typically, the STI process comprises the steps of using a mask to define and pattern a shallow trench in a substrate by an anisotropic etching process, and then filling the shallow trench with oxide for use as a device isolation structure. Since the shallow trench isolation structure has a good isolation effect and its size is scaleable, it is often employed as a device isolation structure. The shallow trench isolation is the preferred isolation technique, especially for the fabrication of a metal oxide semiconductor transistor.
Conventionally, the sidewalls of the shallow trench isolation structure are usually perpendicular to the substrate surface; that is, the corner of the shallow trench isolation structure is a right angle. As a result, high stress occurs at the corner of the shallow trench isolation structure. The stress leads to damage of the silicon lattices in the substrate surface; thus dislocation is generated. In a subsequent step, a gate oxide layer formed on the substrate is not able to form a predetermined thickness because the silicon lattices of the substrate surface are damaged. Therefore, a leakage current occurs at the corner of the shallow trench isolation structure.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method for forming a MOSFET to avoid leakage current while forming a device isolation structure in the process of forming the MOSFET.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming a MOSFET. First, a pad oxide layer and a mask layer are formed on a substrate in sequence, and then the pad oxide layer and the mask layer are patterned to form an opening exposes the substrate. The opening is filled with an epitaxial silicon layer. A surface level of the epitaxial silicon layer is substantially the same as that of the mask layer. Then, the mask layer is removed to expose the pad oxide layer. An oxide layer is formed over the substrate. Next, a portion of the oxide layer is removed to expose the epitaxial silicon layer. Finally, a gate is formed on the epitaxial silicon layer by the conventional method, and source/drain regions are formed in the epitaxial silicon layer.
The feature of this invention is that an epitaxial silicon layer with device isolation structures is formed over the substrate, wherein each device isolation structure is made of oxide. The invention need not etch the substrate for forming a device isolation structure. As a result, the invention not only prevents stress and dislocation generation and avoids leakage current, but also provides an easily method for forming a device isolation structure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5959331 (1999-09-01), Hsu et al.
patent: 6010928 (2000-01-01), Hsu et al.
Le Dung A
Nelms David
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
LandOfFree
Method for forming mosfet does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming mosfet, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming mosfet will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2503293