Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-06-30
1999-11-16
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438303, 438305, H01L 21336
Patent
active
059857277
ABSTRACT:
Disclosed is a low threshold asymmetric MOS device having a pocket region with a graded concentration profile. The pocket region includes a relatively high dopant atom concentration (of the same conductivity type as the bulk region) abutting either the device's source or its drain along the side of the source or drain that faces the device's channel region. The pocket region's graded concentration profile provides a lower dopant concentration near the substrate surface and an increasing dopant concentration below that surface. This provides a relatively low resistance conduction path through the pocket region, while allowing the device's threshold voltage to be somewhat higher at the pocket region. The asymmetric device can also include a counter dopant region located beneath its substrate surface. This forces current to flow in the substrate but just above the region of high counter dopant concentration, where the resistance is relatively low.
REFERENCES:
patent: 4939571 (1990-07-01), Nishizawa et al.
patent: 4949140 (1990-08-01), Tam
patent: 5536959 (1996-07-01), Kellam
patent: 5650340 (1997-07-01), Burr et al.
patent: 5753958 (1998-05-01), Burr et al.
patent: 5773863 (1998-06-01), Burr et al.
R. H. Yan et al., "High Performance 0.1-micron Room Temperature Si MOSFETs", Symposium on VLSI Technology Digest of Technical Papers, pp. 86-87, 1992. Month Unknown.
M. Aoki et al., "0.1-micron CMOS Devices Using Low-Impurity Channel Transistors (LICT)", pp. 9.8.1.-9.8.3, IEDM, 1987. Month Unknown.
Hisao Yoshimura et al., "New CMOS Shallow Junction Well FET Structure (CMOS-SJET) for Low-Power Suppy Voltage", Semiconductor Device Engineering Laboratory, Japan, Proceedings of IEDM, pp. 909-912, 1992. Month Unknown.
James B. Burr et al., "Energy Considerations in Multichip-Module based Microprocessors", IEEE International Conference on Computer Design, pp. 593-600, 1991. Month Unknown.
J. Burr et al., "Ultra Low Lower CMOS Technology", NASA VLSI Design Symposium, pp. 4.2.1-4.2.13, 1991. Month Unknown.
Jim Burr, "Stanford Ultra Low Power CMOS", Symposium Record, Hot Chips V, pp. 7.4.1-7.4.12, Stanford, CA, 1993. Month Unknown.
"A New Lease on Life for Old-Fashioned Chips", Business Week, Science and Technology, pp. 100-101, Dec. 20, 1993.
James B. Burr et al., "A 200mV Self-Testing Encoder/Decoder Using Stanford Ultra-Low Power CMOS", IEEE International Solid State Circuits Conference, 1994. Month Unknown.
Meeting Notes by Dr. James B. Burr et al., Feb. 25, 1994. (After giving talk at an annual Hitachi seminar held in Stanford, CA, Dr. Burr had dinner with M. Nagata, K. Sasaki, H. Hiraki and O.Nishii of Hitachi Corp., and Dr. Burr discussed his work on low threshold voltage COMS devices. During dinner, one of the gentlemen from Hitachi sketched some notes and figures showing possible MOS device structures (Exhibit A). One sketch shown appears to be an NMOS device having "p++" regions under both the source and drain.).
Yoshinori Okumura et al., "Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET Structures for High Current Drivability and Threshold Voltage Controllability", IEEE Transactions on Electron Devices, vol. 39, No. 11, pp. 2541-2552, Nov. 1992.
George A. Sai-Halasz et al., "High Transconductance and Velocity Overshoot in NMOS Devices at the 0.1-micron Gate-Length Level", IEEE Electron Device Letters, vol. 9, No. 9, pp. 464-466, Sep. 1998.
R. Jayaraman et al., "Comparison of High Voltage Devices for Power Integrated Circuits", IEDM, pp. 258-261, 1984. Month Unknown.
Junko Tanaka et al., "A Sub-0.1-micron Grooved Gate MOSFET with High Immunity to Short-Channel Effects", IEEE Transactions on Electronic Devices, vol. 42, No. 3, pp. 537-540, Mar. 1995.
Wen-Ling Margaret Huang et al., "TFSOI Complementary BiCMOS Technology for Low Power Applications", IEEE Transactions on Electronic Devices, vol. 42, No. 3, pp. 506-512, Mar. 1995.
W.R. Hunter et al., "A New Edge-Defined Approach for Submicrometer MOSFET Fabrication", IEEE Electron Device Letters, vol. EDL-2, No. 1, Jan. 1981.
Lebentritt Michael S.
Niebling John F.
Sun Microsystems Inc.
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