Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1991-09-26
1999-07-27
Brown, Peter Toby
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438225, 438230, 438297, 438301, 438439, H01L 218238
Patent
active
059306149
ABSTRACT:
A first conductor for a field shield and a first insulating film are sequentially formed in a predetermined shape on a major surface of a P-type semiconductor substrate through an insulating film. A third insulating film is formed over the semiconductor substrate so as to cover the first conductor and a second insulating film thereon. The third insulating film is anisotropically etched, so that a sidewall insulating film is formed on sidewalls of the first conductor. Second and third conductors respectively serving as gate electrodes of field effect transistors are formed through a fourth insulating film. n-type impurities are implanted into the major surface of the semiconductor substrate utilizing as masks the first insulating film, the sidewall oxide film, the second conductor and the third conductor and are diffused, to form impurity regions. Since the sidewall oxide film is thick, the impurity regions are not overlapped even by diffusion with a portion where the first conductor is projected on the semiconductor substrate. Thus, a threshold voltage of a field shield transistor comprising the first conductor and the impurity regions on both sides thereof is raised, so that isolation characteristics of the field shield is improved.
REFERENCES:
patent: 4455565 (1984-06-01), Goodman et al.
patent: 4486943 (1984-12-01), Ryden et al.
patent: 4561170 (1985-12-01), Doering et al.
patent: 4597824 (1986-07-01), Shinada et al.
patent: 4654691 (1987-03-01), Shirasawa et al.
patent: 4689647 (1987-08-01), Nakagawa et al.
patent: 4696092 (1987-09-01), Doering et al.
patent: 4728617 (1988-03-01), Woo et al.
patent: 4736342 (1988-04-01), Imondi et al.
patent: 5067000 (1991-11-01), Eimori et al.
IEEE Transactions on Electron Devices, vol. 36, No. 4, Apr. 1989 A High-Performance Directly Insertable Self-Aligned Ultra-Rad-Hard and Enhanced Isolation Field-Oxide Technnology for Gigahertz Silicon NMOS/CMOS VLSI, Lalita Manchanda, et al.
Webster's II New Riverside University Dictionary .COPYRGT.1984, p. 1206.
Ogura, et al. "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor," IEEE Elec. Devices, Aug. 1980, pp. 1359-1367.
Eimori Takahisa
Ozaki Hiroji
Satoh Shin-ichi
Tanaka Yoshinori
Wakamiya Wataru
Brown Peter Toby
Mitsubishi Denki & Kabushiki Kaisha
Pham Long
LandOfFree
Method for forming MOS device having field shield isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming MOS device having field shield isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming MOS device having field shield isolation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-891483