Method for forming metal wiring layer of semiconductor device

Details Method for forming metal wiring layer of semiconductor device Method for forming metal wiring layer of semiconductor device

2003-03-20

2004-11-09

Quach, T. N. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S623000, C438S624000, C438S637000

Reexamination Certificate

active

06815331

ABSTRACT:

BACKGROUND
1. Technical Field
The present invention relates to methods for fabricating a semiconductor device, and, more particularly, to methods for forming a metal wiring layer in a semiconductor device through a dual damascene process.
2. Description of Related Art
As the integration density of semiconductor devices increases, a gap width between metal wiring layers in the semiconductor devices decreases. Consequently, it has been necessary to design metal wiring layers having a multi-layered wiring structure. However, parasitic resistance and capacitance existing between adjacent metal wiring layers in a lateral direction or in a vertical direction may affect the performance of the semiconductor devices.
Such parasitic resistance and capacitance components in a metal wiring layer generally cause a decrease in the operating speed, and thus deteriorate the electrical characteristics of the device. Further, the parasitic resistance and capacitance components increase the total power consumption of chips in the semiconductor device and an amount of signal leakage. Accordingly, a need exists to develop a method for forming a multi-layered wiring layer having low parasitic resistance and capacitance in a super-highly integrated semiconductor device.
Typically, a multi-layered wiring structure that has low parasitic resistance and capacitance is formed of a metal having low specific resistance or a dielectric layer having a low dielectric constant. For instance, a metal wiring layer that is formed of a material having low specific resistance such as copper has been studied. It is difficult to form a copper wiring layer by patterning copper using photolithography. Thus, a dual damascene process is commonly used to form such a copper wiring layer.
FIGS. 1 through 5
are cross-sectional views of a metal wiring layer in a semiconductor device formed according to a conventional method. Referring to
FIG. 1
, a stopper layer
104
is formed on a semiconductor substrate
100
, on which a predetermined conductive layer
102
has been formed. An interlayer insulating layer
106
is formed on the stopper layer
104
. Next, a first photoresist pattern
108
is formed on the interlayer insulating layer
106
. The first photoresist pattern
108
comprises a first opening H
1
having a first width W
1
and partially exposing the surface of the interlayer insulating layer
106
. In other words, the interlayer insulating layer
106
is covered with photoresist, and then the photoresist is exposed to light and developed, thereby forming the first photoresist pattern
108
.
Referring to
FIG. 2
, the interlayer insulating layer
106
is etched using the first photoresist pattern
108
as an etching mask until the top surface of the stopper layer
104
is exposed. Thus, a via hole
110
having the first width W
1
is formed in an interlayer insulating layer
106
a
. The first photoresist pattern
108
is removed by a conventional method such as an ashing process.
Referring to
FIG. 3
, a second photoresist pattern
112
is formed on the interlayer insulating layer
106
a
having the via hole
110
. The second photoresist pattern
112
comprises a second opening H
2
having a second width W
2
greater than the first width W
1
and partially exposing the surface of the interlayer insulating layer
106
a
. The second opening H
2
is aligned with the via hole
110
.
Referring to
FIG. 4
, the interlayer insulating layer
106
a
is etched using the second photoresist pattern
112
as an etching mask by a dry etching method. As a result, a wiring region
114
having the second width W
2
is formed in an interlayer insulating layer
106
b
, and a via hole
110
a
having the first width W
1
is formed at the lower part of the wiring region
114
to connect the conductive layer
102
to the wiring region
114
. However, during the etching process of the interlayer insulating layer
106
a
, the stopper layer
104
may be etched with the interlayer insulating layer
106
a
, thereby exposing the conductive layer
102
.
Even though the interlayer insulating layer
106
b
has a high etching selectivity to a stopper layer
104
a
, the stopper layer
104
exposed through the via hole
110
(See
FIG. 3
) is inevitably etched at a predetermined speed during the etching of the interlayer insulating layer
106
a
. Accordingly, after etching of the interlayer insulating layer
106
b
is completed, the exposed stopper layer
104
may be completely etched, and thus the conductive layer may be exposed to an etching atmosphere. If the conductive layer
102
, for example, a copper wiring layer, is exposed to an etching atmosphere, hard polymer (not shown) is formed along sidewalls of the interlayer insulating layer
106
b
. Such hard polymer is difficult to remove. The hard polymer is more easily formed for a case where the interlayer insulating layer
106
a
to be etched is deeper, the stopper layer
104
a
is thinner, and the etching selectivity of the stopper layer
104
a
with respect to the interlayer insulating layer
106
b
is smaller.
Referring to
FIG. 5
, the second photoresist pattern
112
is removed by an ashing process. The ashing process uses an oxygen-based plasma. During the removal of the second photoresist pattern
112
, that is, during the ashing process, the exposed conductive layer
102
may react with oxygen and form a metal oxide layer
116
. The metal oxide layer
116
rapidly increases electrical resistance. Thus, even though the wiring region
114
and the via hole
110
a
are filled with a conductive material, a metal wiring layer (not shown) and the conductive layer
102
cannot be electrically connected to each other, thus causing a lifting phenomenon. Further, since the ashing process using an oxygen-based plasma is performed after forming the wiring region
114
and the via hole
110
a
, the process may damage to the surface of the interlayer insulating layer
106
b
. For instance, H
2
O, OH, CO
2
, and H
2
released during the ashing process stick to the surface of the interlayer insulating layer
106
b
, and thus the dielectric constant of the interlayer insulating layer
106
b
may be rapidly increased.
FIGS. 6 through 10
are cross-sectional views of another metal wiring layer in a semiconductor device formed according to another conventional method. Referring to
FIG. 6
, a stopper layer
204
is formed on a semiconductor substrate, on which a conductive layer
202
has been formed. An interlayer insulating layer
206
is formed on the stopper layer
204
. Next, a first photoresist pattern
208
, which includes a first opening H
1
having a first width W
1
and partially exposing the surface of the interlayer insulating layer
206
, is formed on the interlayer insulating layer
206
. In other words, the interlayer insulating layer
206
is covered with photoresist, and then the photoresist is exposed to light and developed, thereby forming the first photoresist pattern
208
.
Referring to
FIG. 7
, the interlayer insulating layer
206
is partially etched using the first photoresist pattern
208
as an etching mask so that a partial via hole
210
having the first width W
1
is formed in an interlayer insulating layer
206
a
. The first photoresist pattern
208
is removed by a typical method such as an ashing process.
Referring to
FIG. 8A
, a second photoresist pattern
212
is formed on the interlayer insulating layer
206
a
having the partial via hole
210
. The second photoresist pattern
212
comprises a second opening H
2
having a second width W
2
greater than the first width W
1
and partially exposing the surface of the interlayer insulating layer
206
a
. The second opening H
2
is formed to be aligned with the partial via hole
210
. However, photoresist from the second photoresist pattern
212
may remain on the bottom surface of the partial via hole
210
during the forming of the second photoresist pattern
212
on the interlayer insulating layer
206
a
. Since the remaining photoresist will act as a barrier to a subsequent etching process of the interlayer insulating

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