Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-03-14
2002-05-21
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S618000, C438S624000, C438S642000, C438S652000, C438S653000, C257S750000, C257S751000
Reexamination Certificate
active
06391769
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing an integrated semiconductor circuit and an integrated semiconductor circuit fabricated thereby, and more particularly, to a method for forming a metal interconnection and a contact structure fabricated thereby.
2. Description of the Related Art
In general, semiconductor devices include transistors, resistors and capacitors. Metal interconnections are required for interconnecting the semiconductor devices to complete the formation of an integrated circuit. The metal interconnections, which transmit electric signals, must have low electric resistance, and be economical and reliable. Aluminum has been widely used as a material for the metal interconnections.
As semiconductor devices become more highly integrated, the width or thickness of the metal interconnection must be reduced, requiring the size of a contact hole be reduced. As a result, the aspect ratio of the contact hole increases, requiring new methods for completely filling the contact hole with the metal interconnection. A selective chemical vapor deposition (CVD) process has been proposed as a method for completely filling the contact hole having a high aspect ratio with the metal interconnection. The selective CVD process uses the characteristic in which a growth rate of the metal layer on an insulating layer is different from that on a conductive layer.
Conventionally, an interdielectric layer formed on a semiconductor substrate is patterned to form a plurality of contact holes exposing a predetermined area of a lower interconnection interposed between the interdielectric layer and the semiconductor substrate. Then, metal plugs may be formed within the contact holes using the selective CVD process. Here, in the case where at least one of the plurality of contact holes has a depth different from that of the other contact holes, even if all the contact holes have the same diameter, it is difficult to form metal plugs level with the surface of the interdielectric layer in all of the contact holes. In other words, if a metal plug completely filling the deepest contact hole is formed, a metal plug formed within a shallow contact hole will have a protrusion having a height higher than the surface of the interdielectric layer. Therefore, it is difficult to form metal plugs without such a protrusion in a plurality of contact holes having different depths from one another using conventional selective CVD processes.
Also, as the integration density of the semiconductor device increases, the junction depth of a source/drain region of a transistor is reduced. Accordingly, an aluminum layer, used as the metal interconnection, penetrates into the shallow source/drain region, thereby causing a junction spiking phenomenon. To prevent such a junction spiking, a barrier metal layer interposed between the aluminum layer and the source/drain region has been used to suppress the reaction of aluminum atoms of the aluminum layer with silicon atoms of the source/drain region. The barrier metal layer is formed on the entire surface of the resultant structure where the contact holes are formed. Therefore, it is practically impossible to selectively form the metal interconnections only in the contact hole by the selective CVD process since a blanket barrier metal is present on the entire surface of the semiconductor substrate.
SUMMARY OF THE INVENTION
To solve the above problems, the present invention provides a method for forming a metal interconnection capable of selectively forming a metal layer for interconnection uniformly in a contact hole or a groove.
Another objective of the present invention is to provide a contact structure fabricated by the metal interconnection forming method.
According to one embodiment of the present invention for achieving the above objective, an interdielectric layer is formed on a semiconductor substrate. Then, a predetermined region of the interdielectric layer is etched, to form an interdielectric layer pattern having a recessed region. Here, the recessed region may be a contact hole for exposing the predetermined region of the semiconductor substrate or a groove which is shallower than the thickness of the interdielectric layer. The contact hole may be a metal contact hole or a via hole used in a multi-layered metal interconnection technology. When the recessed region is a groove, the metal interconnection is formed through a damascene process. Subsequently, a barrier metal layer, i.e., a titanium nitride (TiN) layer, is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. Here, when the recessed region is the metal contact hole for exposing the predetermined region of the semiconductor substrate, i.e., a source/drain region of a transistor, an ohmic metal layer must be formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed, before forming the barrier metal layer. Then, the barrier metal layer is annealed at a predetermined temperature if necessary, to fill the grain boundary region of the barrier metal layer with oxygen atoms. This is for preventing the diffusion of silicon atoms of the semiconductor substrate through the barrier metal layer. Subsequently, an anti-nucleation layer, e.g., an insulating layer, is selectively formed only on the barrier metal layer formed on the non-recessed region, to thereby expose only the barrier metal layer formed on the sidewalls and the bottom of the recessed region. The insulating layer is for selectively forming a metal interconnection only in the recessed region in a process to be performed later. That is, using a characteristic in which the metal layer is not deposited on the insulating layer, the metal layer used for the metal interconnection is formed by the CVD process. Preferably, the insulating layer is one selected from the group consisting of a metal oxide layer, a metal nitride layer, a SiC layer, a BN layer, a SiN layer, a TaSiO layer and a TiSiO layer.
The metal oxide layer can be formed by selectively forming a layer having excellent oxidation characteristics, i.e., a metal layer, only on the barrier metal layer formed on the non-recessed region, and then exposing the metal layer to air or to O
2
plasma. Also, the metal oxide layer can be formed by loading and oxidizing the resultant structure in a furnace, where the metal layer has excellent oxidation characteristics. Furthermore, the metal oxide layer can be formed by spontaneously oxidizing the resultant structure having a metal layer having excellent oxidation characteristics in a space having a predetermined degree of vacuum. The metal nitride layer, e.g., an aluminum nitride layer, may be formed by selectively forming an aluminum layer only on the barrier metal layer formed on the non-recessed region, and then exposing the aluminum layer to N
2
or NH
3
plasma or performing RTP in an atmosphere of NH
3
and/or N
2
.
Alternatively, the anti-nucleation layer, i.e., the metal oxide layer, may be formed by forming a metal layer exposing the barrier metal layer in the metal contact hole on the resultant structure having the barrier metal layer and then annealing the resultant structure having the metal layer. Here, the annealing process is the same as that performed directly after forming the barrier metal layer. Therefore, an oxygen stuffing process performed directly after forming the barrier metal layer can be omitted. Here, the barrier metal layer and the metal layer exposing the barrier metal layer in the contact hole are preferably in-situ formed.
Preferably, a metal layer for forming the metal oxide layer is an Al layer, a Cu layer, a Au layer, a Ag layer, a W layer, a Mo layer, a Ta layer, a Zr layer, a Sr layer, a Mg layer, a Ba layer, a Ca layer, a Ce layer, a Y layer, a Cr layer, a Co layer, a Ni layer or a Ti layer. Also, the metal layer may be a metal alloy film containing one selected from the group consisting of Al, Au, Ag, W, Mo and Ta, and at least one selected from the
Choi Gil-heyun
Kim Byung-hee
Lee Jong-myeong
Lee Sang-in
Lim Hyun-seok
Berezny Nema
Bowers Charles
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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