Method for forming metal capacitors with a damascene process

Details Method for forming metal capacitors with a damascene process Method for forming metal capacitors with a damascene process

2001-06-15

2002-01-15

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S687000, C438S688000

Reexamination Certificate

active

06338999

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to the formation of an integrated circuit including capacitors. In particular, the present invention relates to a method for forming metal capacitors with a damascene process.
2. Description of the Related Art
Capacitors are integrated in various integrated circuits. For example, capacitors can be used as decoupling capacitors to provide improved voltage regulation and noise immunity for power distribution. Capacitors also have wide applications in analog/logic, analog-to-digital, mixed signal, radio frequency circuits and so on.
A conventional method of manufacturing a semiconductor apparatus including a capacitor
20
that is formed of metal-insulator-metal layers is described with reference to FIGS.
1
A~
1
D. As shown in
FIG. 1A
, an aluminum layer is deposited on an insulator
12
which contains interconnections and is formed on a silicon substrate having devices (not shown) thereon and therein. The aluminum layer is then patterned by masking and etching to form wires
14
a
and
14
b
. As shown in
FIG. 1B
, an insulator
16
with a tungsten plug
18
(hereafter “W-plug”) used to connect the aluminum wire
14
a
and the to-be-formed capacitor is formed on the aluminum wires
14
a
and
14
b
and the insulator
12
. As shown in
FIG. 1C
, a first conductive plate
21
, a dielectric layer
22
and a second conductive plate
23
are sequentially deposited on the insulator
16
and the W-plug
18
, and then patterned by masking and etching to obtain a capacitor
20
. The first conductive plate
21
, the bottom electrode, is connected with the aluminum wire
14
a
through the W-plug
18
. Another insulator
26
is deposited on the insulator
16
and the capacitor
20
. The insulators
16
and
26
are patterned and W-plug
28
a
and W-plug
28
b
are formed therein. As shown in
FIG. 1D
, an aluminum layer (not shown) is deposited on the insulator
26
and the W-plugs
28
a
and
28
b
. The aluminum layer is then patterned by masking and etching to form wires
34
a
and
34
b
. The aluminum wire
34
a
is connected with the second conductive plate
23
through the W-plug
28
a
. The aluminum wire
34
b
is connected with the aluminum wire
14
b
through the W-plug
28
b.
The above-mentioned method for integrating the capacitor
20
into an integrated circuit requires several masking and etching steps to form the capacitor
20
, which may increase overall fabrication costs. Moreover, if a greater capacitance of the plane capacitor
20
is required, a greater area of the plane capacitor
20
is needed. This will sacrifice the spaces between the capacitor
20
and the nearby wires and make scaling down difficult. Furthermore, a drop height exists between the capacitor area and the non-capacitor area, resulting in an uneven topography of the insulator
26
.
A method of manufacturing a capacitor while simultaneously forming a dual damascene via is disclosed in U.S. Pat. No. 6,025,226. In the '226 patent, a conductor which is used to form a bottom electrode is deposited in the openings for the via and capacitor. However, the conductor should be sufficiently thick to fill the via opening and sufficiently thin to not planarize the capacitor opening. It is difficult to form such a conductor.
Besides, the aluminum used to fabricate the traditional interconnections cannot satisfy the trends of enhanced integration and speed of data transmission. Copper (Cu) has high electric conductivity to reduce RC delay and can be substituted for aluminum as conducting wires. The use of copper as the conducting wires requires the use of processes, that is, damascene processes, because copper cannot be patterned by etching processes. This is because the boiling point of copper chloride (CuCl
2
) produced by copper and the chlorine plasma usually used to etch metal is relatively high, about 1500° C. Therefore, Cu processes should be used to fabricate an integrated circuit including a capacitor.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming metal capacitors with a damascene process.
It is another object of the invention to reduce the number of masking and etching steps in manufacturing an integrated circuit including a capacitor.
Yet another object of the invention is to reduce the cost of manufacturing an integrated circuit including a capacitor.
It is a further object of the invention to reduce the drop height existing between the capacitor area and the noncapacitor area.
Still another object of the invention is to provide easily controllable processes of manufacturing an integrated circuit including a capacitor.
Another object of the invention is to use the Cu processes to fabricate the integrated circuit including capacitors to reduce RC delay.
The present invention provides a method for forming a metal capacitor with a damascene process. Before fabricating the thin-film capacitor, a first Cu wire and a second Cu wire, surrounded with a barrier layer and a first sealing layer, are prepared in a first insulator. A second insulator is formed on the sealing layer. An opening is formed in the second insulator and the sealing layer and the first Cu wire is exposed. A first metal layer, a third insulator and a second metal layer are conformally formed, in turn, in the opening on the second insulator. A chemical mechanical polishing process is executed to remove the first metal layer, the third insulator and the second metal layer until the second insulator is exposed; thereby, a bottom electrode, a capacitor dielectric and an upper electrode are formed in the opening respectively. The bottom electrode is connected to the first Cu wire. A fourth insulator having dual damascene patterns is formed over the capacitor and the second insulator.
These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.


REFERENCES:
patent: 6008084 (1999-12-01), Suug et al.
patent: 6008085 (1999-12-01), Sung et al.
patent: 6025226 (2000-02-01), Gambino et al.

Affiliated with

Also associated with

Rating

Method for forming metal capacitors with a damascene process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming metal capacitors with a damascene process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming metal capacitors with a damascene process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2825250