Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-14
2002-10-08
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C428S208000, C428S208000
Reexamination Certificate
active
06461906
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for forming memory array, and more particularly relates to a method for forming memory cells by using a dummy polysilicon layer.
2. Description of the Prior Art
A conventional nitride read only memory (NROM) cell is shown as FIG.
1
. The cell comprises a substrate
10
which is implanted to form a source
12
and a drain
14
therein and a structure
16
of oxide
itride/oxide (ONO) is placed thereon. The structure
16
of oxide
itride/oxide has a nitride layer
17
between a first silicon oxide layer
18
and a second silicon oxide layer
20
. Furthermore, a gate conductor
22
is placed on the structure
16
of oxide
itride/oxide. A channel
15
between the source
12
and the drain
14
is formed below the structure
16
of oxide
itride/oxide.
The nitride layer
17
provides a retaining electron mechanism for programming memory cells. In particular, when the source
12
, the drain
14
and the gate conductor
22
are supplied with a voltage, electrons may flow forward to the drain
14
. According to the hot electron injection effect, some hot electrons may penetrate through the first silicon oxide layer
18
below the nitride layer
17
, and may be collected into the nitride layer
17
particularly when the first silicon oxide layer
18
is very thin. In view of known technologies, the nitride layer
17
may retain the accepted electrons
24
of an aggregation region near the drain
14
. The aggregated electrons
24
observably raises a threshold voltage of neighboring memory cell channel near the drain
14
, which is higher than a threshold voltage of the left channel
15
.
During reading period, the primal source electrically exchanges with the primal drain. It means that the source
12
is supplied with a high voltage while the drain
14
is with a low voltage. When the higher voltage reads the memory cell in the existence of the aggregated electrons
24
, it may prohibit the cell from being at a conductivity state. On the other hand, in absence of the aggregated electrons
24
, the reading voltage of the gate conductor
22
may overcome a lower threshold voltage and the channel
15
may reverse to conduct.
FIG. 2
is a side view of a row in a conventional memory array which uses the memory cell mentioned above. A plurality of bit lines
12
are sources or drains of the memory cell, which together with the oxide devices of the bit lines
50
are isolated each another by the structures of the oxide
18
, the nitride
17
and the oxide
20
. Polysilicon
60
for forming word lines is over the structures of the oxide
18
, the nitride
17
, the oxide
20
and the oxide devices of the bit lines
50
. The word lines above the structures of the oxide
18
, the nitride
17
and the oxide
20
are gate structures of the memory cell. In the memory array, the oxide device of bit lines
50
are formed by the method of local oxidation of silicon (LOCOS) so that the bit lines below are not formed by the method of self-aligned silicide for reducing resistance. Furthermore, the higher thermal budget may be improved during the ongoing process.
SUMMARY OF THE INVENTION
The main object of the invention is to provide a dummy layer for protecting gate oxide and structure of oxide
itride/oxide from damage during forming bit lines. In the present invention, the dummy layer may be used for defining the bit lines of self-aligned silicide for reducing resistance.
Another object of the invention is to make the bit lines have little thermal budget so that they may be helpful for scale micro-shrinkage and can be made the smaller space of cell and the channel length. There are two steps for reducing the thermal budget. The peripheral gate oxide and structure of oxide
itride/oxide are formed earlier than the formation of bit lines such that the thermal budget of memory array is reduced. The second step is to form bit line oxide by the method of high density plasma deposition or spin-on-glass that can reduce the thermal budget of memory array, rather than conventional thermal oxidation.
In order to achieve previous objects of the invention, a method for forming a memory cell comprises providing a substrate first, and forming a dielectric layer on the substrate. In the present invention, the dielectric structure comprises a structure of oxide
itride/oxide or an oxide layer. The structure of oxide
itride/oxide may be formed nitride read-only memory, while the oxide layer may be formed mask read-only memory. Next as a key step of the present invention, a first polysilicon layer and a silicon nitride layer are sequentially formed on the dielectric layer. Then a bit line pattern is defined on the substrate to form a bit line. The formation of bit line comprises etching the partial dielectric layer. Next, a plurality of spacers are formed on the sidewalls of the first polysilicon layer and the silicon nitride layer, and bit lines are for forming salicide by a method of self-aligned silicide. The following is another key step of the present invention. A word line oxide layer is formed by the method of high density plasma chemical vapor deposition, or spin-on glass process. Then the oxide layer is etched to stop on the silicon nitride layer by the chemical mechanic polishing or etching back method. Finally, the silicon nitride layer is removed and word lines are then formed by depositing a second polysilicon layer.
REFERENCES:
patent: 5098855 (1992-03-01), Komori et al.
patent: 5175120 (1992-12-01), Lee
patent: 6174758 (2001-01-01), Nachumovsky
Chaudhari Chandra
Macronix International Co. Ltd.
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