Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-09-28
2002-07-23
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S233000, C438S587000, C438S672000
Reexamination Certificate
active
06423627
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to electronic circuits and more particularly to a method for forming memory array and periphery contacts using a same mask.
BACKGROUND OF THE INVENTION
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Solid state devices are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, solid state devices are very reliable because they have no moving parts, but are based on the movement of charge carriers.
Solid state devices may be transistors, capacitors, resistors and other semiconductor devices. Typically, such devices are fabricated on and in a substrate and interconnected to form memory arrays, logic structures, timers and other integrated circuits. One type of memory array is a dynamic random access memory (DRAM) in which memory cells retain information only temporarily and are refreshed at periodic intervals. Despite this limitation, DRAMs are widely used because they provide low cost per bit of memory, high device density and feasibility of use.
DRAMs typically include a memory array and a peripheral circuit that provides addressing and other functions for the memory array. The trend toward denser DRAM arrays has led to the use of additional mask levels and processing steps to form self-aligned contacts (SACTs) within the DRAM. The use of separate mask levels significantly increases the manufacturing time and cost of DRAMs.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for forming memory array and periphery contacts is provided that substantially eliminates or reduces the disadvantages or problems associated with previously developed methods. In particular, the present invention provides a method that uses a same mask to form memory array and periphery contacts in a dynamic random access memory (DRAM) or other suitable electronic circuit.
In one embodiment of the present invention, contacts for an integrated circuit are formed by providing a substrate that has at least two access line structures for a memory array and a periphery structure for a peripheral circuit to the memory array. A first insulative layer is formed outwardly of the substrate, the access line structures, and the periphery structure. A contact area of the periphery structure is exposed through the first insulative layer while maintaining the first insulative layer over at least a contact overlap portion of the access line structures. A second insulative layer is formed outwardly of the substrate, the access line structures, the periphery structure, and the first insulative layer. A self-aligned contact hole overlapping the contact overlap portion of the access line structures and a periphery contact hole overlapping the contact area of the periphery structure are formed through the second insulative layer with a same mask. A self-aligned contact is formed in the self-aligned contact hole and a periphery contact is formed in the periphery contact hole.
Technical advantages of the present invention include providing an improved method for forming contacts for an electronic circuit. In particular, an insulative layer is etched to expose a contact area of the periphery structure, while maintaining the insulative layer over the access line structures. Accordingly, a separate mask and etch process is not needed to expose the periphery contact area, and a same mask and etch process is used to form memory array contact holes and periphery contact holes. As a result, the integrated circuit may be fabricated more efficiently both in terms of cost and processing time.
Other technical advantages of the present invention will be readily apparent to one skilled in the art from the following figures, descriptions and claims.
REFERENCES:
patent: 5718800 (1998-02-01), Juengling
patent: 5909616 (1999-06-01), Dennison
patent: 5949145 (1999-09-01), Komuro
patent: 6071799 (2000-06-01), Park et al.
patent: 6146949 (2000-11-01), Wu
patent: 6165878 (2000-12-01), Haruhana et al.
patent: 11-284138 (1999-10-01), None
Carter Duane E.
Hwang Ming J.
Brady W. James
Brophy Jamie L.
Hoel Carlton H.
Jr. Carl Whitehead
Telecky , Jr. Frederick J.
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