Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-13
2001-11-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S240000, C438S241000, C438S242000, C438S250000, C438S251000, C438S252000, C438S254000, C438S255000, C438S256000, C438S393000, C438S394000, C438S395000, C438S396000, C438S397000, C438S398000, C438S399000
Reexamination Certificate
active
06323083
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a capacitor of a semiconductor device, and more particularly, to a method for forming a lower electrode structure of a capacitor, wherein a metal such as titanium is reacted with the upper portion of a polysilicon plug connected to the substrate through an insulation layer, to form a silicide contact for electrical contact with the lower electrode.
2. Description of the Background Art
Any capacitor, such as that used for a memory cell of a semiconductor device, basically includes a pair of electrodes separated by a dielectric layer. In a semiconductor device comprising a gate, source, and drain, the lower electrode is connected to an active region of the device through a contact hole.
In the development of memory devices having increased memory capacity, an increased cell capacitance must be secured for ever-diminishing areas. In order to obtain increased cell capacitance within a given area, one of three conditions should be satisfied:
the dielectric layer should have an increased dielectric constant, either by way of dielectric material selection or by subsequent processing of the dielectric layer, e.g., by a thermal treatment process; the effective area between the plates (electrodes) should increased in some manner, for example, by utilizing a three-dimensional dimensional electrode structure; or the capacitor should be fabricated such that the distance between the plates is decreased, meaning that the dielectric layer is made thinner. There is a practical limit to decreasing the thickness of the dielectric layer, and three-dimensional structures are highly complex formations, which have their own limitations.
As one example of the aforementioned thermal treatment process to improve the dielectric layer, an oxide annealing process may be performed at a high temperature of approximately 700° C. to enhance properties of the dielectric layer. Such a process, however, also produces an undesirable oxidation effect, i.e., a natural oxide film grows on the electrode surfaces, which causes a reduction in the resultant capacitance. The oxidation of conductive surfaces occurs due to oxide gases reaching the lower electrode by seeping under the dielectric layer, in particular, at the edges thereof.
Meanwhile, in coping with the tendency for the contact hole to have a higher aspect ratio due to decreased areas (hole size) in more highly integrated semiconductor devices, in many cases, the capacitor needs to be provided with a conductive plug for connecting the active region and the lower electrode. The plug is formed by filling the contact hole, which is formed in a relatively thick insulation layer, with a doped polysilicon, thus establishing an interface for electrical connection between the upper surface of the plug and the lower surface of the lower electrode.
However, in such a capacitor, i.e., one having such a plug, the plug interface may become oxidized during the above thermal treatment process, which degrades the adhesive force between the lower electrode and the plug, especially in the event of imperfect alignment conditions between the polysilicon plug and the lower electrode. This degraded adhesion causes a lifting phenomenon, whereby the plug may become separated from the lower electrode during subsequent processing. Such separation reduces the overall capacitance and degrades the electrical characteristics of the capacitor, such as leakage current and reliability, while decreasing the yield rate of a semiconductor device having such a capacitor.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a method for forming an improved lower electrode structure of a capacitor of a semiconductor device, which overcomes the problems of the conventional art.
It is another object of the present invention to provide a method for forming a lower electrode structure of a capacitor of a semiconductor device, which improves the electrical connection between a conductive plug and the lower electrode.
It is yet another object of the present invention to provide a method for forming a lower electrode structure of a capacitor of a semiconductor device, which inhibits the formation of a natural oxide film at the interface of a conductive plug and the lower electrode, even when a high-temperature oxidizing process is performed with respect to the dielectric layer.
It is still another object of the present invention to provide a method for forming a lower electrode structure of a capacitor of a semiconductor device, which improves the electrical characteristics of the capacitor.
It is a further object of the present invention to provide a method for forming a lower electrode structure of a capacitor of a semiconductor device, which increases the yield rate of the semiconductor device.
It is still a further object of the present invention to provide a method for forming a lower electrode structure of a capacitor of a semiconductor device, in which the reliability of the capacitor is improved.
It is still yet another object of the present invention to provide a method for forming a lower electrode structure of a capacitor of a semiconductor device, in which the leakage current of the capacitor is reduced.
To achieve these and other advantages and in accordance with the purposed of the present invention, as embodied and broadly described herein, there is provided a method for forming a lower electrode structure of a capacitor of a semiconductor device, comprising the steps of: forming an active region in a semiconductor substrate; forming an insulation layer atop the semiconductor substrate having the active region formed therein; forming a contact hole in the insulation layer, the contact hole exposing the active region; forming a conductive plug connected to the active region through the contact hole, the conductive plug having an upper contact surface; forming a silicide contact on the upper contact surface of the conductive plug; forming a lower to electrode layer in electrical contact with the silicide contact, by depositing titanium aluminum nitride on the insulation layer; and patterning the lower electrode layer to form a lower electrode having an upper surface.
According to the above method, the silicide layer is formed on the upper portion of the plug, and the lower electrode made of a titanium aluminum nitride having a high oxidation inhibiting characteristic is formed atop the insulation layer to be connected to the silicide layer. This oxidation is inhibited at the upper portion and the lower portion of the lower electrode, even though a high-temperature oxidizing process is performed to improve properties of the dielectric layer.
REFERENCES:
patent: 5231306 (1993-07-01), Meikle et al.
patent: 5525542 (1996-06-01), Maniar et al.
patent: 5729054 (1998-03-01), Summerfelt et al.
patent: 5851896 (1998-12-01), Summerfelt
patent: 6153490 (2000-11-01), Xing et al.
patent: 6235631 (2001-05-01), Russell
Lee Sang-hyeob
Park Dae-gyu
Hyundai Electronic Industries Co. Ltd.
Kennedy Jennifer M.
Niebling John F.
Oliff & Berridge PLC.
LandOfFree
Method for forming lower electrode structure of capacitor of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming lower electrode structure of capacitor of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming lower electrode structure of capacitor of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2575943