Method for forming lower electrode of capacitor

Details Method for forming lower electrode of capacitor Method for forming lower electrode of capacitor

1995-11-17

1998-10-20

Niebling, John

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

438240, H01L 2100, H01L 218242

Patent

active

058245634

ABSTRACT:
A method for forming the lower electrode of a capacitor used for fabricating a 1-Gbit or above DRAM, using a material having a high dielectric constant, is used in a method for manufacturing a storage capacitor of a VLSI semiconductor device. The lower electrode, which is to be in contact with a high dielectric film, is formed to have a triple-structured storage node pattern. The lowest layer of the lower electrode is formed with TiN which serves as a barrier against the diffusion of impurities from a lower substrate. The middle layer of the lower electrode is formed with RuO.sub.2 which is easy to pattern. The uppermost layer of the lower electrode is formed with Pt which has excellent leakage current properties.

REFERENCES:
patent: 5392189 (1995-02-01), Fazan et al.
patent: 5407855 (1995-04-01), Maniar et al.
patent: 5489548 (1996-02-01), Nishioka et al.
S. Wolf and R.N. Tauber, "Silicon Processing for the VLSI Era vol. 1--Process Technology," Lattice Press, pp. 335-336, 523, 528 & 541-542, 1986.
S. Wolf, "Silicon Processing for the VLSI Era vol. 2--Process Integration," Lattice Press, p. 230, 1990.

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