Method for forming low-voltage CMOS transistors with a thin laye

Details Method for forming low-voltage CMOS transistors with a thin laye Method for forming low-voltage CMOS transistors with a thin laye

1997-06-12

1999-09-14

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438210, 438238, 438275, H01L 218238, H01L 218234

Patent

active

059535997

ABSTRACT:
The low-voltage, e.g., 2.5-volt, transistors that support the logic operations of a CMOS device are formed to have a thin layer of gate oxide, while the high-voltage, e.g., 3.3 or 5-volt, transistors that support the analog operations of the device are formed to have a thick layer of gate oxide in a cost-effective process flow that requires only one additional masking step over a conventional double-poly CMOS process.

REFERENCES:
patent: 5304503 (1994-04-01), Yoon et al.
patent: 5432114 (1995-07-01), O
patent: 5468666 (1995-11-01), Chapman
patent: 5489547 (1996-02-01), Erdeljac et al.
patent: 5716863 (1998-02-01), Arai
patent: 5723355 (1998-03-01), Chang et al.
patent: 5759887 (1998-06-01), Ito et al.

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