Method for forming LDD CMOS using double spacers and large-tilt-

Details Method for forming LDD CMOS using double spacers and large-tilt- Method for forming LDD CMOS using double spacers and large-tilt-

1998-07-14

2000-08-08

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257336, 257346, 257408, 257900, 257215, 257387, 257327, 257204, 257338, 257300, 257351, H01L 31062, H01L 2976, H01L 2994

Patent

active

061005614

ABSTRACT:
A method of forming an integrated circuit device, and in particular a CMOS integrated circuit device, having an improved lightly doped drain region. The methods include the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectric over each P type well and N type well regions. The present LDD fabrication methods then provide a relatively consistent and easy method to fabricate CMOS LDD regions with N type and P type implants at a combination of different dosages and angles using first and second sidewall spacers, with less masking steps and improved device performance.

REFERENCES:
patent: 4949136 (1990-08-01), Jain
patent: 5606191 (1997-02-01), Wang

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