Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2009-10-08
2010-12-21
Landau, Matthew C (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21429, C257S334000, C438S268000
Reexamination Certificate
active
07855115
ABSTRACT:
A field effect transistor (FET) is formed as follows. A trench is formed in a silicon region. An oxidation barrier layer is formed over a surface of the silicon region adjacent the trench and along the trench sidewalls and bottom. A protective layer is formed over the oxidation barrier layer inside and outside the trench. The protective layer is partially removed such that a portion of the oxidation barrier layer extending at least along the trench bottom becomes exposed and portions of the oxidation barrier layer extending over the surface of the silicon region adjacent the trench remain covered by remaining portions of the protective layer.
REFERENCES:
patent: 6437386 (2002-08-01), Hurst et al.
patent: 6861296 (2005-03-01), Hurst et al.
patent: 7009247 (2006-03-01), Darwish
patent: 7648877 (2010-01-01), Andrews
patent: 2004/0082162 (2004-04-01), Kang et al.
patent: 200707589 (2007-02-01), None
patent: WO 2007/001988 (2007-01-01), None
International Search Report and Written Opinion of the International Searching Authority mailed on Jul. 7, 2008 for PCT/US06/23819 mailed on Jul. 7, 2008; 10 pages.
Notice of Allowance for U.S. Appl. No. 11/166,356 mailed on Sep. 22, 2009; 6 pages.
Advisory Action for U.S. Appl. No. 11/166,356 mailed on Sep. 2, 2009; 3 pages.
Final Office Action for U.S. Appl. No. 11/166,356 mailed on Jun. 22, 2009; 11 pages.
Non-Final Office Action for U.S. Appl. No. 11/166,356 mailed on Mar. 10, 2009; 9 pages.
Final Office Action for U.S. Appl. No. 11/166,356 mailed on Jun. 20, 2008; 8 pages.
Non-Final Office Action for U.S. Appl. No. 11/166,356 mailed on Sep. 18, 2007; 10 pages.
Restriction Requierement for U.S. Appl. No. 11/166,356 mailed on Jun. 22, 2007; 5 pages.
Preliminary Report on Patentability for Application No. PCT/US2006/023819, mailed on May 7, 2009, 7 pages.
Chinese Office Action for Application No. 200680022794.5, dated Mar. 29, 2010, 26 pages.
Fairchild Semiconductor Corporation
Landau Matthew C
McCall Shepard Sonya D
Townsend and Townsend / and Crew LLP
LandOfFree
Method for forming laterally extending dielectric layer in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming laterally extending dielectric layer in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming laterally extending dielectric layer in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4186610