Method for forming junction leakage monitor for mosfets with sil

Details Method for forming junction leakage monitor for mosfets with sil Method for forming junction leakage monitor for mosfets with sil

1999-01-25

2000-12-26

Bowers, Charles

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

438 14, H01L 2166

Patent

active

061658073

ABSTRACT:
A method for forming and using silicide test structures to monitor and evaluate the quality of a semiconductive junction after the formation of a silicide layer over the junction is described. Two specially designed test structures are formed for in-line testing in the kerf of an integrated circuit wafer. The test structures comprise a silicide region formed over a diffusion region which is formed concurrently with diffusion and silicide regions which form contacts of the integrated circuit dice. The test structures are fitted with probe pads connected to semiconductive element of the junction region. A first structure is designed to measure bulk junction leakages, has the silicide contact layer spaced away from the junction edge. A second structure, designed to measure edge related junction leakage phenomena, has a serpentine edge to which the silicide layer extends and a plurality of interior openings which serve as EMMI windows. After the silicide contact layers have been formed, and the excess refractory metal has been etch away, the structures are subjected to junction leakage measurement. Differences in junction leakage between the two structures indicate the leakage mechanisms as well as their bulk or edge relationship. Further testing by EMMI is used to confirm and supplement the leakage measurements.

REFERENCES:
patent: 4100486 (1978-07-01), Casowitz et al.
patent: 4305760 (1981-12-01), Trudel
patent: 4592921 (1986-06-01), Hieber et al.
patent: 5451529 (1995-09-01), Hsu et al.
patent: 5637186 (1997-06-01), Liu et al.
patent: 5759871 (1998-06-01), Hause et al.

Affiliated with

Also associated with

Rating

Method for forming junction leakage monitor for mosfets with sil does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming junction leakage monitor for mosfets with sil, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming junction leakage monitor for mosfets with sil will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-993780