Method for forming isolation in flash memory wafer

Details Method for forming isolation in flash memory wafer Method for forming isolation in flash memory wafer

1998-02-05

2004-10-26

Weiss, Howard (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S296000, C438S424000, C257S321000, C257S510000

Reexamination Certificate

active

06808988

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to computer flash memory systems, and more particularly to systems and methods for isolating flash memory elements.
BACKGROUND OF THE INVENTION
Flash memory chips or wafers are used in many applications, including hand held computing devices, wireless telephones, and digital cameras. In flash memory, a flash memory core containing a matrix of memory elements is surrounded by a periphery containing peripheral elements. The elements in the core assume physical states which represent bits of data. Consequently, by configuring the core elements appropriately, data (such as preselected telephone numbers in a wireless telephone or digital images in a digital camera) may be stored in the core and subsequently read by detecting the physical state of one or more core elements.
To enable the individual memory elements of a flash memory wafer to maintain the physical state with which they have been programmed, each memory region must be isolated from its neighboring regions. In the case of the peripheral regions, isolation is achieved by a method referred to in the art as local oxidation silicon, or “LOCOS”. LOCOS isolation requires disposing an inactive silicon oxide insulator between neighboring active regions. While acceptable for isolating peripheral regions, however, LOCOS isolation is less than desirable for memory core cell isolation. This is because it is desirable to minimize the distance between core cells to increase memory density, and the silicon in LOCOS isolation tends to encroach on the core memory cells, thereby decreasing core cell (and, hence, memory) density.
Accordingly, a process that renders closely spaced memory core cells, referred to in the art as “self-aligned” cells, has been developed. Self-aligned memory core cells are isolated from each other by shallow trenches that are etched into the silicon substrate of the core, between adjacent memory cells.
The memory cells between the trenches are established by one or more layers of polysilicon material. More specifically, a first layer of polysilicon is deposited onto a tunnel oxide that is grown on a silicon substrate, and the first layer of polysilicon is then etched, typically accompanied by or followed by isolation trench etching. Then, after the isolation trenches have been formed, the gates of the memory cells are established by depositing an interpoly dielectric layer on the wafer and a second layer of polysilicon on the interpoly dielectric layer, followed by etching the second layer of polysilicon as appropriate to form the desired memory element stack pattern and establish the gates of the memory cells. As recognized by the present invention, however, establishing the polysilicon gates of the memory cells after trench isolation complicates the fabrication process. As further recognized herein, a method can be provided for simplifying the relatively costly fabrication process.
Accordingly, it is an object of the present invention to provide a method and system for isolating core memory cells of a flash memory device. Another object of the present invention is to provide a method and system for isolating core memory cells of a flash memory device which does not require gate formation after trench etching. Still another object of the present invention is to provide a method and system for isolating core memory cells of a flash memory device that is easy to use and cost effective.
BRIEF SUMMARY OF THE INVENTION
A process is disclosed for making a flash memory core having source and drain regions. The process includes the steps of providing at least one silicon substrate, and establishing at least one tunnel oxide layer on the substrate. Plural stacks are established on the tunnel oxide layer, with each stack including a first polysilicon layer. At least one interpoly dielectric layer is formed on at least some of the stacks. Then, the method includes depositing at least one second polysilicon layer on at least a portion of the interpoly dielectric layer, such that plural memory cell control gates are established. After the control gates have been established, isolation trenches are established in the substrate.
In a preferred embodiment, the trenches are formed by etching such that at least adjacent drain regions of the memory core are separated from each other by a respective isolation trench. Likewise, the step of establishing the stacks is accomplished at least in part by dry etching.
As envisioned by the preferred embodiment described herein, the method further includes depositing a field oxide material on at least portions of the silicon substrate prior to the step of forming at least one interpoly dielectric layer. Additionally, channel stop dopant is implanted in the silicon substrate prior to the step of depositing a field oxide material. A flash memory wafer made according to the present method, and a computing device incorporating the flash memory wafer, are also disclosed.
In another aspect, a flash memory wafer includes a core memory region including at least one silicon substrate, and plural memory cells in the core memory region. Each memory cell has a gate established by at least two layers of polysilicon, and at least some regions of the core memory region are separated by isolation trenches that are formed after the control gates of the memory cells have been formed.
In still another aspect, a method for making a flash memory wafer includes establishing plural memory cell control gates on at least one silicon substrate, and forming isolation trenches on the substrate after the control gates have been established.
Other features of the present invention are disclosed or apparent in the section entitled: “DETAILED DESCRIPTION OF THE INVENTION.”


REFERENCES:
patent: 4698900 (1987-10-01), Esquivel
patent: 5087584 (1992-02-01), Wada et al.
patent: 5110753 (1992-05-01), Gill et al.
patent: 5469383 (1995-11-01), McElroy et al.

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