Method for forming interconnects on semiconductor substrates...

Details Method for forming interconnects on semiconductor substrates... Method for forming interconnects on semiconductor substrates...

2002-07-08

2003-05-27

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S751000, C257S762000, C438S622000

Reexamination Certificate

active

06570255

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a method for forming an electrical conductor in an electronic structure and more particularly, relates to a method for forming interconnects in a semiconductor structure and structures formed.
BACKGROUND OF THE INVENTION
The technology of making metal conductors to provide for vias, lines and other recesses in semiconductor chip structures, flat panel displays and package applications has been developed in the past decade. For instance, in developing interconnection technology for very-large-scale-integrated (VLSI) structures, aluminum has been utilized as the primary metal source for contacts and interconnects in semiconductor regions or devices located on a single substrate. Aluminum has been the material of choice because of its low cost, good ohmic contact and high conductivity. However, pure aluminum thin-film conductors have undesirable properties such as a low melting point which limits its use to low temperature processing and possible diffusion into the silicon during annealing which leads to contact and junction failure, and poor electromigration resistance. Consequently, a number of aluminum alloys have been developed which provided advances over pure aluminum.
Recently developed ULSI technology has placed more stringent demands on the wiring requirements due to the extremely high circuit densities and faster operating speeds required of such devices. This leads to higher current densities in increasingly smaller conductor lines. As a result, higher conductance wiring is desired which requires either larger cross-section wires for aluminum alloy conductors or a different wiring material that has a higher conductance. The obvious choice in the industry is to develop the latter which includes pure copper for its desirable high conductivity.
In the formation of ULSI interconnection structures such as vias and lines, copper can be deposited into such recesses to interconnect semiconductor regions or devices located on the same substrate. However, copper is known to have problems in semiconductor devices. The electromigration phenomenon occurs when the superposition of an electric field onto random thermal diffusion in a metallic solid causes a net drift of atoms in the direction of electron flow. This can lead to degradation in interconnect reliability. Diffusion of copper atoms into the silicon substrate or ILD can also cause device failure and poor reliability. In addition, pure copper does not adhere well to oxygen-containing dielectrics such as silicon dioxide and polyimide. To fully utilize copper in interconnection technology, the adhesion, diffusion and electromigration properties of copper must be improved control.
A schematic of an enlarged, cross-sectional view of an electronic structure that utilizes conventional interconnections made of a copper or copper alloys is shown in FIG.
1
. The electronic structure
10
contains two levels of copper interconnections
12
,
16
and one stud level
14
illustrating a copper wiring structure formed in a Damascene process on a pre-fabricated device
20
. The device
20
is built on a semi-conducting substrate
24
. As shown in
FIG. 1
, a typical Damascene level is first fabricated by the deposition of an ILD stack
26
. The ILD stack
26
is then patterned and etched using standard lithograph and dry etch techniques to produce a desired wiring or via pattern. The process is then followed by the metal depositions of a thin adhesion/diffusion barrier liner
18
and copper or copper alloy metallurgy
12
wherein a bottom capping layer such as silicon nitride layer
28
is used as a diffusion barrier/etch stop which is previously deposited on top of the device
20
to protect against copper diffusion. After the copper or copper alloy interconnection
12
is formed, a top cap layer such as a silicon nitride layer
32
is deposited and used as an etch stop layer for defining the next level copper interconnection
14
. After a second level ILD stack
34
is deposited, a recess for an interconnect is etched into the ILD stack
34
and the silicon nitride layer
32
.
An interlevel copper alloy stud
14
with liner
22
is then deposited by a technique similar to that used in depositing the first level copper or copper alloy interconnection
12
. A variety of metal deposition techniques can be used for filling the trench or via. These techniques include a collimated sputtering process, an ionized sputtering process, a hollow cathode magnetron sputtering process, a chemical vapor deposition process, an electroless plating process and an electrolytic plating process. Other techniques such as a co-deposition method in which copper and an alloying element are co-deposited can also be used in forming the copper alloys. For instance, the co-deposition methods include co-sputtering, “alloy plating”, sequential plating of different materials with subsequent annealing, chemical vapor deposition, sequential chemical vapor deposition and co-evaporation. After the completion of the interlevel copper alloy stud
14
, another similar process is repeated to form the second level copper interconnection
16
with liner
24
in a third ILD stack layer
38
. An etch stop layer
36
such as silicon nitride is utilized between the stud and the second level interconnections. Finally, a top capping layer
42
is deposited on top of the copper wiring structure
10
for protecting the device from the environment.
More recently, void-free and seamless conductors are produced by electroplating copper from plating baths that contain additives. The capability of the electroplating method to superfill structural features without leaving voids or seams is unique and superior to that of other deposition techniques. Electrolytic copper plating techniques used in damascene structures can be defect-free if the deposited seed layer is continuous and has a uniform thickness even in the deepest area of the structural feature to be plated. The copper seed layer is typically deposited by a physical vapor deposition technique or other techniques over a barrier layer that prevents diffusion of copper into the insulator such as Ta, TaN, TiN or TaSiN. When the deposited seed layer is too thin at the bottom or near-bottom walls of a structural feature, plating does not occur and a void is created.
In order to eliminate the non-continuous deposition problem occurring during sputtering of a copper seed layer, a seed layer of a larger thickness is normally deposited. The deposition of a thick seed layer helps to eliminate the plated Cu voiding problem, however, it creates another one of equal or even greater significance, i.e. poor electromigration resistance in the resultant structure. The poor electromigration resistance of the structure is caused by the fact that the seed layer itself has weak electromigration resistance when compared to the much higher electromigration resistance of the plated film. It is also noted that in future generations of chips, the seed layer will contribute an increasing part of the total structure based on the decreasing dimensions of the features and the inability to decrease the thickness of the seed layer proportionally for reason stated above as well as the thickness uniformity requirements in electrolytic plating.
The Cu damascene process consists of the formation of trenches and vias in a dielectric material (such as SiO
2
), which stops at an etch-stop shown as layer
46
in
FIG. 2
filling the vias and trenches with a metal stack containing a barrier layer followed by Cu and then removing the excess metal from the field region typically by chemical/mechanical polishing. This is shown in
FIGS. 2A and 2B
, for a single damascene structure
50
and a dual damascene structure
40
, respectively. When Cu damascene interconnects are produced using plated Cu, typically a physical vapor deposition Cu film
26
(seed layer) is deposited on the barrier layer to improve the substrate conductivity and to allow for uniform Cu plating. The as-plated Cu
44
is fine grained (0.05-0.2

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