Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-15
2001-01-23
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S643000, C438S648000, C438S663000
Reexamination Certificate
active
06177341
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming interconnections in semiconductor devices and, more specifically, relates to a method for forming a plug in a contact window or a via hole to connect two conductive layers respectively disposed above and below the hole in semiconductor devices.
2. Description of the Prior Art
As integrated circuit technology develops, methods of fabrication for most devices in a limited space is a task that needs to be overcome. A contact window or a via hole has been widely applied to form an interconnection of two conductive layers in semiconductor devices. Since the sizes of the contact window and via hole are shrinking due to process requirements, one of the most important tasks is how to form a good conductive plug to connect two conductive layers without obstructing conductivity, as the sizes of the contact window and via hole become smaller.
One of conventional methods for forming interconnections in semiconductor devices is first forming a hole in a dielectric layer on a semiconductor substrate. A first conductive layer, which can be a potion of the semiconductor substrate being implanted with an impurity or can be any conductive layer, is disposed under the dielectric layer. A contact layer, which is usually made of titanium, is deposited on inner surface of the hole and a barrier layer, which is usually made of titanium nitride, is deposited on the contact layer. Then, a second conductive layer fills the hole to form a conductive plug. Finally, a third conductive layer is formed on the second conductive layer, thereby, the third conductive layer connects the first conductive layer by the second conductive layer to form the interconnections in semiconductor devices.
In the above conventional method, the contact layer is used to effectively connect the second conductive layer and dielectric layer, which would otherwise have poor contacts, and to allow the second conductive layer to have good ohmic contact with the underneath first conductive layer. For example, when the first conductive layer contains silicon, the titanium of the contact layer will react with the silicon to produce a titanium silicon compound, which forms an effective ohmic contact. The barrier layer is used to protect the contact layer from being damaged by reactive gas, which is applied in a consequent depositing step of the second conductive layer. For example, the second conductive layer is usually made of a tungsten compound, and tungsten hexafluoride, which is applied in forming a tungsten plug, will produce reactive fluoride ions to attack the contact layer.
Since the conventional method cannot prevent the contact layer from fluoride ion attacks due to poor deposition of the barrier layer, and cannot avoid problems which result from the loss of the contact layer, such as peeling of the contact layer and barrier layer, and volcano effects which occur due to a rise in deposition, a rapid thermal annealing process is introduced to the method. U.S. Pat. No. 5,591,672 discloses an annealing process which introduces ammonia and raises the annealing temperature to above 700° C., after depositing a titanium contact layer and titanium nitride barrier layer in the contact window. This allows ammonia to react with an exposed portion of the titanium contact layer and to form titanium nitride which repels fluoride ion attacks. The contact window is then filled with a metal layer.
The annealing process introduces nitrogen gas at a flow rate of 20 liters per minute at standard state into a thermal annealing chamber and loads therein a wafer, when the chamber temperature reaches 350° C. to 450° C. A first temperature raising step commences: the annealing chamber temperature is rapidly raised to between 575° C. and 625° C. and lasts for 60 seconds. Next, a second temperature raising step commences: the temperature is rapidly raised to between 700° C. and 745° C. The gas introduced into the chamber for both steps is ammonia, at a flow rate between 2 and 5 liters per minute. Lastly, nitrogen, at a flow rate of 20 liters per minute at standard state, is introduced into the chamber to rapidly lower the chamber temperature to below 350° C. and the wafer is removed from the chamber.
Although the method may ease volcano effects, some problems remain unsolved. The annealing process of wafers in the rapid thermal annealing chamber is characterized by the introduction of ammonia, two temperature raising steps, and an annealing temperature higher than 700° C. The introduction of ammonia results in the disadvantage of requiring ammonia waste gas disposal treatment, since the ammonia is an air pollutant and is not allowed to be directly expelled into the environment without treatment. Furthermore, the high temperature may damage the conductive layer under the contact hole, for example impurities of a source and/or a drain of a field effect transistor, may cause device failures and can cause a reduction in production yields.
U.S. Pat. No. 5,591,671 discloses a method for forming interconnections. Although the method uses a high temperature process, the high temperature process is carried out after the deposition of the titanium contact layer and titanium nitride barrier layer, and the filling of a metal layer in the contact window. The reason why the high temperature process is carried out after the filling of metal layer in the contact window is to prevent the contact layer and barrier layer from thermal oxidation. The method can not avoid conventional problems such as volcano effects. Moreover, the high temperature process is carried out in a conventional furnace, which raises and lowers the temperature slowly to prevent a quartz tube in the furnace from being broken. The temperature raising and lowering rates are about 4 to 5° C. per minute, which is a slower rate than that of a rapid thermal process. A preferred embodiment of the method is by raising the temperature of the furnace, which is full of nitrogen, from 450° C. to between 500° C. and 550° C. The step of raising the temperature requires ten to sixty minutes to complete.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for forming interconnections in semiconductor devices. The method is to fill a small contact window or via hole to interconnect two conductive layers in semiconductor devices. In order to achieve high quality interconnections at a relatively low temperature, for avoiding thermal damage of the conductive layers, the present invention discloses an effective rapid thermal annealing process which raises temperature rapidly. The temperature is raised by a simple step of using pure nitrogen after a step of depositing a contact layer and a barrier layer and before a step of filling a conductive layer in the contact window. Consequently, the use of ammonia which requires disposal treatment is avoided, production efficiency is increased, and the cast of waste gas treatment is greatly reduced.
In order to achieve the above object and to avoid the disadvantages of the conventional methods, the present invention discloses a method for forming interconnections in semiconductor devices. The method comprises the following steps,
Providing a semiconductor substrate and forming a first conductive layer on the semiconductor substrate; forming a dielectric layer on the first conductive layer; forming a first hole through the dielectric layer, wherein the bottom of the first hole contacts the first conductive layer; forming a contact layer on the dielectric layer, and on the contact surface of the first hole and the first conductive layer, wherein the first hole is reduced to a second hole; forming a barrier layer on the contact layer, wherein the second hole is reduced to a third hole;
Carrying out a rapid thermal annealing process, which comprises the following steps: placing the semiconductor substrate, which is at an ambient temperature, into a quartz heating chamber, wherein the chamber is filled with nitrogen gas at a first flow rate; redu
Quach T. N.
Vanguard International Semiconductor Corporation
Wood Herron & Evans L.L.P.
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