Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-02-22
2001-08-28
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S773000, C257S776000
Reexamination Certificate
active
06281586
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an integrated semiconductor circuit configuration having conductor tracks or interconnects that run in at least two different planes, in which conductor tracks in at least one of the planes are provided in close proximity and essentially parallel to one another.
During the fabrication of integrated semiconductor circuit configurations, such as semiconductor memories for example, if, by way of example, conductor tracks run closely adjacent and parallel to one another and one of those conductor tracks is interrupted, it is possible for so-called proximity effects to occur. Those effects ultimately result in a conductor track exhibiting a critical location in such a region, at which the conductor track can become unstable and even tend toward an interruption. That instability is explained below with reference to FIG.
4
.
FIG. 3
shows how a discontinuity affects a conductor track.
If such discontinuities are present on both sides of a conductor track, then such a conductor track may become constable, and it may even break.
Such critical locations of conductor tracks need not necessarily be due only to so-called proximity effects. Conductor tracks can also be guided in certain ways, having to do especially with curvatures having a small radius of curvature, that can lead to such critical locations.
It goes without saying that such critical locations are highly undesirable, which is why the geometrical dimensions of the conductor tracks are often enlarged at those locations. However, such a procedure has the disadvantage of causing the conductor tracks and the spacings between them to thus inevitably be enlarged, which is at odds with the constant striving to miniaturize integrated semiconductor circuit configurations.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated semiconductor circuit configuration having stabilized conductor tracks, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and in which instabilities of conductor tracks at critical locations can be reliably avoided.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor circuit configuration, comprising conductor tracks having a given layout and running in at least two different planes, the conductor tracks in at least one of the planes disposed in close proximity and substantially parallel to one another, and the conductor tracks having a dummy contact disposed underneath the conductor tracks at critical locations dictated by the given layout.
The integrated semiconductor circuit configuration according to the invention thus provides a surprisingly simple solution to the above problem of critical locations especially due to the proximity effect. At such locations, the conductor tracks have a dummy contact situated underneath them in a simple manner. The dummy contact can lead as far as an underlying metalization plane without establishing an electrical connection there. As a result, the conductor track has a sufficient cross section in the region of the critical location, so that any instability of the conductor track and any interruption thereof are reliably prevented.
In accordance with another feature of the invention, the dummy contacts are provided at critical locations which are dictated by an interruption of one of two closely adjacent, parallel conductor tracks.
In accordance with a concomitant feature of the invention, the conductor tracks have a width of approximately 150 to 250 nm and a spacing from one another on the order of magnitude of approximately 130 to 180 nm.
Therefore, in the case of the integrated semiconductor circuit configuration according to the invention, dummy contacts are provided at critical locations of conductor tracks. These dummy contacts increase the cross sections of the conductor track at these critical locations, with the result that it is no longer possible for instabilities of the conductor track to occur or even for the latter to break. Increased electromigration susceptibilities are reliably avoided.
The use of the dummy contacts thus makes it possible to provide layouts having critical geometries, that is to say particularly small structures, with the result that the invention promotes further miniaturization of integrated semiconductor circuit configurations.
The present invention affords advantages in a particularly advantageous manner in so-called damascene and dual damascene metalization systems of integrated circuits, since in these systems, the dummy contacts result not only in a local widening of the geometry of the conductor track but also in a local increase in the line cross section.
If appropriate, the invention can also be used in an advantageous manner in other lithographically defined metalization systems, and not just for integrated circuits.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as being embodied in an integrated semiconductor circuit configuration having stabilized conductor tracks, it is nevertheless not intended to be limited to the illustrated details, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 4729063 (1988-03-01), Matsuo et al.
patent: 5625232 (1997-04-01), Numata et al.
patent: 5847466 (1998-12-01), Ito et al.
patent: 0692824A2 (1996-01-01), None
Feurle Robert
Schneider Helmut
Dickey Thomas L.
Flynn Nathan
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
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