Method for forming interconnect bumps on a semiconductor die

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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438614, 438615, 438616, 438617, 29840, 29843, H01L 2144

Patent

active

061071803

ABSTRACT:
A method of forming an interconnect bump structure (32, 33). Under Bumb Metalization 11 (UBM) comprising a chrome layer (16), a copper layer (36), and a tin layer (40) is disclosed. In one embodiment, eutectic solder (45) is then formed over the UBM (11) and reflowed in order to form the interconnect bump stucture. In another embodement, a lead standoff (46) is formed over the UBM (11) before the formation of the eutectic solder (48).

REFERENCES:
patent: 5466635 (1995-11-01), Lynch et al.
patent: 5470787 (1995-11-01), Greer
patent: 5937320 (1999-08-01), Andricacos et al.
D.O.Powell et al., 1993 IEEE, "Flip-Chip on FR-4 Integrated Circuit Packaging", pp. 182-186.
T.Y.Wu, et al., 1996 Electronic Components and Technology Conference, "Materials and Mechanics Issues in Flip-chip Organic Packaging", pp. 524-534.
Flipchip Technologies, Delco/K&S Joint Venture web page with UBM description--http://www.flipchip.com/process.html, "Get bumped", pp. 1-2.
Soichi Honma, et al., "Effectiveness of Thin Film Barrier Metals for Eutectic Solder Bumps", 6 pgs.
Goran Matijasevic, et al., Copper-Tin Multilayer Composite Solder, Dept. of Electrical and Computer Engineering, University of California, Irvine, CA, pp. 264-273, IEPS Proceedings Sep. 12, 1993 San Diego CA.
Eric, Jung, et al., "The Influence of NiSn Intermetallics on the Performance of Flip Chip Contacts Using a Low-Cost Electroless Nickel Bumping Approach", 1996 Proceesings of Int'l. Electronics Pkg. Conf., International Electron Packaging Society, Edina MN, pp. 14-25..
Kevin Hussey, et al., Motorola MMTG MPU Product Analysis, Reliability and Quality Assurance, Product Analysis Report #r000047, 4 pgs.

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