Method for forming integrated circuit transistors using sacrific

Details Method for forming integrated circuit transistors using sacrific Method for forming integrated circuit transistors using sacrific

1997-05-30

2000-02-08

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438223, H01L 21336

Patent

active

060227826

ABSTRACT:
An improved processing technique results in a structure which maximizes contact area by eliminating a sidewall spacer used to form LDD regions. A sacrificial spacer is provided during processing to form the LDD regions, and is then removed prior to further processing of the device. A sidewall spacer is then formed in a self-aligned contact from a later deposited oxide layer used as an interlevel dielectric. This leaves only a single oxide sidewall spacer alongside the gate electrode, maximizing the surface area available for the self-aligned contact itself.

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