Method for forming integrated circuit structure

Details Method for forming integrated circuit structure Method for forming integrated circuit structure

1996-04-25

1998-03-10

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438197, 438238, 438294, 438296, H01L 218242

Patent

active

057260842

ABSTRACT:
A integrated circuit structure and a method of fabrication thereof are provided. In particular, fully planarized, trench isolated semiconductor regions, e.g. comprising doped polysilicon, are provided in an integrated circuit substrate. These polysilicon regions have a smooth surface, substantially coplanar with the substrate surface, provided by chemical mechanical polishing. The near zero topography substrate provides for formation thereon of integrated circuit structures including e.g. capacitors, resistors, thin film capacitors, and interconnects, in the polysilicon trench regions at the same process level as devices formed in the semiconductor substrate. Thus a simple and flexible process for formation of improved device structures is provided, compatible with known Bipolar, CMOS and Bipolar-CMOS processes.

REFERENCES:
patent: 3484311 (1969-12-01), Benzing
patent: 3578515 (1971-05-01), Borrello et al.
patent: 3579058 (1971-05-01), Armgarth
patent: 4758531 (1988-07-01), Beyer et al.
patent: 4839309 (1989-06-01), Easter et al.
patent: 4886762 (1989-12-01), Boland et al.
patent: 5275974 (1994-01-01), Ellul et al.
patent: 5298450 (1994-03-01), Verret
patent: 5302541 (1994-04-01), Akazawa
patent: 5316978 (1994-05-01), Boyd et al.
patent: 5352923 (1994-10-01), Boyd et al.
patent: 5362669 (1994-11-01), Boyd et al.
patent: 5394000 (1995-02-01), Ellul et al.
patent: 5407846 (1995-04-01), Chan
patent: 5411913 (1995-05-01), Bashir et al.
patent: 5477071 (1995-12-01), Hamamoto et al.
patent: 5508531 (1996-04-01), Ha

Affiliated with

Also associated with

Rating

Method for forming integrated circuit structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming integrated circuit structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming integrated circuit structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-138838