Method for forming integrated circuit capacitor and memory

Details Method for forming integrated circuit capacitor and memory Method for forming integrated circuit capacitor and memory

2000-11-16

2003-04-29

Cao, Phat X. (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S118000, C438S396000, C438S397000, C438S398000

Reexamination Certificate

active

06555431

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to electronic devices, and more specifically to semiconductor integrated circuit capacitors and methods of fabrication.
BACKGROUND OF THE INVENTION
Increasing demand for semiconductor memory and competitive pressures require higher density integrated circuit dynamic random access memories (DRAMs) based on one-transistor, one-capacitor memory cells. But scaling down capacitors with the standard silicon oxide and nitride dielectric presents problems including decreasing the quantity of charge that may be stored in a cell. Consequently, alternative dielectrics with dielectric constants greater than those of silicon oxide and nitride are being investigated. Various dielectric materials are available, such as tantalum pentoxide (dielectric constant about 25 versus silicon nitride's dielectric constant of about 7) as described in Ohji et al., “Ta
2
O
5
capacitors dielectric material for Giga-bit DRAMs,” IEEE IEDM Tech. Dig. 5.1.1 (1995); lead zirconate titanate (PZT), which is a ferroelectric and supports nonvolatile charge storage (dielectric constant of about 1000), described in Nakamura et al., “Preparation of Pb(Zr,Ti)O
3
thin films on electrodes including IrO
2
, 65 Appl. Phys. Lett. 1522 (1994); strontium bismuth tantalate (also a ferroelectric) described in Jiang et al. “A New Electrode Technology for High-Density Nonvolatile Ferroelectric (SrBi
2
Ta
2
O
9
) Memories,” VLSI Tech. Symp. 26 (1996); and barium strontium titanate (dielectric constant about 500), described in Yamamichi et al., “An ECR MOCVD (Ba,Sr)TiO
3
based stacked capacitor technology with RuO
2
/Ru/TiN/TiSi
x
storage nodes for Gbit-scale DRAMs,” IEEE IEDM Tech. Dig. 5.3.1 (1995), Yuuki et al., “Novel Stacked Capacitor Technology for 1 Gbit DRAMs with CVD-(Ba,Sr)TiO
3
Thin Films on a Thick Storage Node of Ru,” IEEE IEDM Tech. Dig. 5.2.1 (1995), and Park et al., “A Stack Capacitor Technology with (Ba,Sr)TiO
3
Dielectrics and Pt Electrodes for 1 Giga-Bit density DRAM, VLSI Tech. Symp. 24 (1996). Also see Dietz et al.,” Electrode influence on the charge transport through SrTiO
3
thin films, 78 J. Appl. Phys. 6113 (1995), (describes electrodes of Pt, Pd, Au, and so forth on strontium titanate); U.S. Pat. No. 5,003,428 (PZT and barium titanate), U.S. Pat. No. 5,418,388 (BST, SrTiO
3
, PZT, etc.), and U.S. Pat. No. 5,566,045 (thin Pt on BST).
These alternative dielectrics are typically deposited at elevated temperatures and in an oxidizing ambient. As a result, an oxygen-stable bottom electrode material such as platinum or ruthenium oxide is used. Platinum, however, readily forms a silicide when in direct contact with silicon, and further is not a good barrier to oxygen due to fast diffusion down the platinum grain boundaries. In U.S. Pat. No. 5,504,041, Summerfelt uses a conductive nitride barrier layer beneath a platinum electrode to inhibit diffusion of oxygen to an underlayer susceptible to oxidation. Another problem with platinum electrodes is that the adhesion of platinum to silicon dioxide, silicon nitride, and other common interlayer dielectric materials is poor. Platinum structures that are patterned and etched tend to debond during subsequent processing. U.S. Pat. Nos. 5,489,548; 5,609,927; and 5,612,574 propose the use of an adhesion layer to prevent the debonding of the platinum electrode.
Some of these alternative dielectrics, such as PZT, BST, and SBT are ferroelectrics, and hence may be used as the storage element in ferroelectric non-volatile RAMs (FRAM). An FRAM cell is similar to a DRAM cell, except that the polarization of the ferroelectric material is used to indicate the data content of the cell in an FRAM, while electrical charge in the material indicates the data content of the cell in a DRAM. The charge in the DRAM dissipates, while the polarization of the material is non-volatile.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the invention, there is disclosed a method for etching a feature in a platinum layer overlying a second material without substantially etching the second material. The method includes the the steps of: forming an adhesion-promoting layer between the platinum layer and the second material; forming a hardmask layer over the platinum layer; patterning and etching the hardmask layer in accordance with desired dimensions of the feature; and etching portions of the platinum layer not covered by the hardmask layer, the etching stopping on the adhesion-promoting layer. In further embodiments the adhesion-promoting and hardmask layers are Ti—Al—N including at least 1% of aluminum.
In accordance with another preferred embodiment of the invention, there is disclosed a method for etching platinum. The method includes the steps of: forming a Ti—Al—N hardmask layer over the platinum; patterning and etching the Ti—Al—N hardmask layer with a chlorine-bearing etchant to form a desired pattern; and etching the platinum with an oxygen-bearing etchant.
An advantage of the inventive concepts is that platinum, which has historically been difficult to pattern and etch, is capable of being etched to fine features and with steep sidewall profiles.


REFERENCES:
patent: 5231306 (1993-07-01), Meikle et al.
patent: 5418388 (1995-05-01), Okudaira et al.
patent: 5504041 (1996-04-01), Summerfelt
patent: 5930639 (1999-07-01), Schuele et al.

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