Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – By application of corpuscular or electromagnetic radiation
Reexamination Certificate
1999-02-22
2002-05-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
By application of corpuscular or electromagnetic radiation
C438S305000, C438S308000, C438S763000, C438S795000, C438S952000
Reexamination Certificate
active
06395624
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a method for forming semiconductor devices using Projection Gas-Immersion Laser Doping.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
One new method that shows promise in reducing the cost and complexity of manufacturing integrated circuits is the use of Projection Gas-Immersion Laser Doping (PGILD) developed at Lawrence Livermore National Laboratory. The PGILD process reduces the need for normal photoresist processing during impurity doping. This allows for the elimination of multiple process steps and the associated equipment.
In particular, the PGILD process allows dopants to be selectively incorporated into a substrate without photoresist masking. PGILD uses a high-intensity, excimer laser beam for selectively exposing a wafer in an ambient containing the dopant atoms in gas phase above the wafer. The selective exposure exposes those portions of the wafer where impurities are desired. In the exposed portions of the wafer, light is absorbed by the silicon, heating the surface and allowing the dopant atoms to diffuse into the exposed portions of the wafer.
The PGILD process offers many advantages over conventional processing. First, because photoresist masking is not required, process complexity is significantly reduced. Second, the PGILD process can be used to form relatively abrupt p-n junctions of varying depth because of the higher liquid phase diffusion resulting from the PGILD process when compared to normal solid phase diffusion used in conventional processes. Third, the dopant atoms incorporated directly into the substrate are electrically active without requiring the additional anneals required by conventional processes. This, coupled with the relatively low energy required by the PGILD laser makes it a relatively low temperature technique, reducing the impact on the thermal budget when compared to conventional doping techniques.
The push for ever increasing device densities is particularly strong in CMOS technologies, such as the in the design and fabrication of field effect transistors (FETs). FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.)
The PGILD process has been proposed as method to improve the fabrication of FETs. In particular, the PGILD processes has been a proposed solution to provide the source/drain doped regions for FETs. One disadvantage to this proposed usage of the PGILD process is the amount of heat absorbed by the transistor and the difficulty in dissipating this heat. In particular, the laser used in the PGILD process heats the gate stack. This gate stack, typically made from a conductor such as polysilicon, absorbs heat from the laser and dissipates the heat into the underlying substrate. If the gate stack is unable to effectively dissipate the absorbed heat it can experience significant degradation and loss of continuity.
Typically, the problems with excessive heat absorption and insufficient heat dissipation are localized over areas where thicker oxide between the gate stack and the underlying substrate exists. For example, in modern FET devices shallow trench isolation (STI) is formed over non active areas of the chip. Thus, while sufficient heat dissipation can occur at areas of the gate stack over gate oxide, effective heat dissipation is prevented at areas of the gate stack over the STI. This heat absorption can then cause the gate stack to deform, resulting in morphological degradation due to temperatures near the melting point of silicon. These problems caused by the heat absorption have prevented the widespread adoption of the PGILD process, and thus prevents its other benefits from being available.
Thus, there is a need for improved methods of FET fabrication that allows new doping technologies such as PGILD to be effectively incorporated and used.
DISCLOSURE OF INVENTION
Accordingly, the present invention provides a novel method of forming semiconductor devices that utilizes Projection Gas-Immersion Laser Doping (PGILD) process that overcomes the disadvantages of the prior art methods. In particular, the preferred method applies a reflective coating over features before the application of the PGILD laser. The reflective coating lowers the amount of heat absorbed by the features, improving the reliability of the fabrication process.
The preferred method is particularly applicable to the fabrication of field effect transistors (FETs). In this application, a gate stack is formed, and a reflective coating is over the gate stack. An anti-reflective coating (ARC) is then applied over the reflective coating. The anti-reflective coating reduces variability of the photolithographic process used to pattern the gate stack. After the gate stack is patterned, the anti-reflective coating is removed, leaving the reflective coating on the gate stack. The PGILD process can then be used to form source/drain doped regions on the transistors. The reflective coating reduces the amount of heat absorbed by the gate stack, and thus provides an improved method for fabricating transistors.
The foregoing and other advantages and features of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.
REFERENCES:
patent: 4343832 (1982-08-01), Smith et al.
patent: 5114876 (1992-05-01), Weiner
patent: 5126165 (1992-06-01), Akihama et al.
patent: 5130263 (1992-07-01), Possin et al.
patent: 5316969 (1994-05-01), Ishida et al.
patent: 5386798 (1995-02-01), Lowndes et al.
patent: 5604138 (1997-02-01), Lee et al.
patent: 5612235 (1997-03-01), Wu et al.
patent: 5696011 (1997-12-01), Yamazaki et al.
patent: 5817550 (1998-10-01), Carey et al.
patent: 5908307 (1999-06-01), Talwar et al.
patent: 5955759 (1999-09-01), Ismail et al.
patent: 5962195 (1999-10-01), Yen et al.
Kurt H. Weiner and Somit Talwar, “Self Aligned Silicide Formation Using Gas Immersion Laser Annealing (GILA)”, An Ultratech Stepper technical brief, Mar. 3, 1997.
Kurt H. Weiner and Somit Talwar, “Ultrashallow Junction Formation Using Projection Gas Immersion Laser Doping (PGID)”, A Verdant Technologies technical brief, Aug. 20, 1997.
Bruce James A.
Mann Randy W.
International Business Machines - Corporation
Niebling John F.
Pompey Ron
Schmeiser Olsen & Watts
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