Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-03-13
2000-03-28
Saadat, Mahshid
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438211, 438257, 438260, 438263, 438264, 438299, 438301, 257309, 257317, 257321, H01L 21336
Patent
active
060431245
ABSTRACT:
The present invention proposes a method for fabricating a high speed and high density nonvolatile memory cell. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited on the substrate and then the tunnel oxide region is defined by a standard photolithography process followed by an anisotropic etching. A high temperature steam oxidation process is used to grow a thick thermal oxide on the non-tunnel region. After removing the masking silicon nitride layer, the n+ impurity ions is implanted to form the source and drain, and a thermal annealing is performed to recover the implantation damage and to drive in the doped ions. Next, the pad oxide film is etched back and an ultra-thin undoped .alpha.-Si, or HSG-Si, film is deposited. A thermal oxidation process is carried out to convert the undoped .alpha.-Si or HSG-Si into textured tunnel oxide. Finally, the first n+ doped polysilicon film which serves as the floating gate, the interpoly dielectric such as ONO, the second n+ doped polysilicon film which serves as the control gate are sequentially formed, and the memory cell is finished.
REFERENCES:
patent: 4404577 (1983-09-01), Cranford, Jr. et al.
patent: 5429966 (1995-07-01), Wu et al.
patent: 5683923 (1997-11-01), Shimizu et al.
patent: 5796140 (1998-08-01), Tomioka
patent: 5960285 (1999-09-01), Hong
Albert Bergemont et al., Low Voltage NVG.TM.: A New High Performance 3 V/5 V Flash Technology for Portable Computing and Telecommunications Applications, IEEE Transactions on Electron Devices, vol. 43, No. 9, Sep. 1996, pp. 1510-1517.
H. Shirai et al., A 0.54 .mu.m.sup.2 Self-Aligned, HSG Floating Gate Cell (SAHF Cell) for 256Mbit Flash Memories, 1995 IEEE, pp. 653-656.
Yosiaki S. Hisamune et al., A High Capacitive-Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories, 1993 IEEE, pp. 16-22.
Shye Lin Wu et al., Characterization of Thin Textured Tunnel Oxide Prepared by Thermal Oxidation of Thin Polysilicon Film on Silicon, IEEE Transactions on Electron Devices, vol. 43, No. 2, Feb. 1996, pp. 287-294.
Christopher J. Hegarty et al., Enhanced Conductivity and Breakdown of Oxides Grown on Heavily Implanted Substrates, Solid-State Electronics, vol. 34, No. 11, 1991, pp. 1207-1213.
Richards N. Dean
Saadat Mahshid
Texas Instruments--Acer Incorporated
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