Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-17
2001-04-03
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000, C438S239000, C438S238000, C438S381000, C438S396000, C438S003000
Reexamination Certificate
active
06211008
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method of fabricating a capacitor, and more particularly, to a method of fabricating a capacitor having large capacitor surface area on a minimum chip area in the fabrication of an integrated circuit device.
(2) Description of the Prior Art
Capacitors are critical components in the integrated circuit devices of today. As the technology in the semiconductor industry grows, the physical geometry of the semiconductor devices shrink. While maintaining the required capacitance, it is desirable to form the capacitor on as small a chip area as possible, thus reducing cell size.
U.S. Pat. No. 5,942,787 to Gardner teaches a method of using polysilicon spacers as a mask for making very small polysilicon features. U.S. Pat. No. 5,912,492 to Chang et al shows a capacitor having spacers over a FOX. U.S. Pat. No. 5,909,621 to Hsia et al, U.S. Pat. No. 5,854,105 to Tseng, and U.S. Pat. No. 5,712,202 to Liaw et al show capacitor processes using spacers of various types. U.S. Pat. No. 5,595,928 to Lu et al shows a process for forming polysilicon pillar capacitors.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to provide an effective and very manufacturable process for fabricating a capacitor in the fabrication of integrated circuits.
Another object of the present invention is to provide a method for fabricating a high-density high-capacity capacitor in the fabrication of integrated circuits.
A further object of the present invention is to provide a method for fabricating a high-density high-capacity capacitor in a process compatible with the double poly layer process in the fabrication of integrated circuits.
In accordance with the objects of this invention, a method for fabricating a high-density high-capacity capacitor is achieved. A dielectric layer is provided overlying a semiconductor substrate. A sacrificial layer is deposited overlying the dielectric layer and patterned to form a pattern having a large surface area within a small area on the substrate. Spacers are formed on sidewalls of the patterned sacrificial layer. Thereafter, the sacrificial layer is removed. A bottom capacitor plate layer is conformally deposited overlying the spacers. A capacitor dielectric layer is deposited overlying the bottom capacitor plate layer. A top capacitor plate layer is deposited overlying the capacitor dielectric layer and pattern to complete fabrication of a high-density high-capacity capacitor.
Also in accordance with the objects of this invention, another method for fabricating a high-density high-capacity capacitor is achieved. A dielectric layer is provided overlying a semiconductor substrate. A sacrificial layer is deposited overlying the dielectric layer and patterned to form a pattern having a large surface area within a small area on said substrate. A bottom capacitor plate layer is deposited overlying the patterned sacrificial layer and etched to leave spacers on sidewalls of the patterned sacrificial layer. Thereafter, the sacrificial layer is removed. A capacitor dielectric layer is conformally deposited overlying the bottom capacitor plate layer. A top capacitor plate layer is deposited overlying the capacitor dielectric layer and patterned to complete fabrication of a high-density high-capacity capacitor.
REFERENCES:
patent: 5065273 (1991-11-01), Rajeevakumar
patent: 5075817 (1991-12-01), Butler
patent: 5595928 (1997-01-01), Lu et al.
patent: 5712202 (1998-01-01), Liaw et al.
patent: 5854105 (1998-12-01), Tseng
patent: 5909621 (1999-06-01), Hsia et al.
patent: 5912492 (1999-06-01), Chang et al.
patent: 5942787 (1999-08-01), Gardner et al.
patent: 5972722 (1999-10-01), Visokay et al.
patent: 5994197 (1999-11-01), Liao
patent: 6037216 (2000-03-01), Liu et al.
Gerung Henry
Pradeep Yelehanka Ramachandramurthy
Qian Jun
Yu Jie
Chartered Semiconductor Manufacturing Ltd.
Pike Roseman L. S.
Saile George O.
Smith Matthew
Yevsikov V.
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