Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-01
2001-02-13
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S398000, C438S665000, C438S491000, C438S532000
Reexamination Certificate
active
06187630
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for forming integrated circuit device. More particularly, the present invention relates to a method for forming hemispherical silicon grains on designated areas of a silicon layer.
2. Description of Related Art
As structural dimensions of a semiconductor device continue to shrink, each device occupies a much smaller substrate area. However, the surface area of some devices, for example, the capacitor of a dynamic random access memory (DRAM), must have at least a minimum surface area for capacitative coupling.
Otherwise, interference from nearby circuits or devices can affect its operation and the number of refreshes can increase as well. One method of increasing the surface area of a capacitor is to form hemispherical silicon grains on the lower electrode surface of the capacitor. Hence, the overall surface area of the capacitor per unit area of silicon chip surface can be increased so that the amount of electric charges stored in a capacitor is raised.
FIGS. 1A and 1B
are schematic, cross-sectional views showing the steps according to a conventional method of forming hemispherical silicon grains on the lower electrode surfaces of a capacitor. The storage capacity of the capacitor is thereby increased.
First, as shown in
FIG. 1A
, a substrate
100
having a field effect transistor
104
thereon is provided. Then, a dielectric layer
110
is formed over the substrate
100
and the field effect transistor
104
. Thereafter, a contact opening
112
that exposes a source/drain region
108
is formed in the dielectric layer
110
. In the subsequent step, a doped amorphous silicon layer
113
having a thickness of about 6000 Å is deposited, completely fills the contact opening
112
, and covers the dielectric layer, as well.
Next, the doped amorphous silicon layer
113
is patterned to form a doped amorphous silicon layer
113
a
as shown in
FIG. 1B
, thereby forming the bulk of the lower electrode of a capacitor. After that, hemispherical silicon grains are formed on the exposed surface of the doped amorphous silicon layer
113
a
in order to increase the overall surface area of the lower electrode.
In the aforementioned method, a very thick layer of doped amorphous silicon layer
113
has to be deposited so that a proper electrode structure for the capacitor is formed. However, the rate of deposition of amorphous silicon is rather low, and hence a lot of time is spent in the process of depositing doped amorphous silicon material onto the dielectric layer
110
to a sufficient thickness. The longer the process of depositing amorphous silicon, the slower the production rate of the semiconductor device is.
Furthermore, a long deposition tends to increase the chance of microcrystallization inside the amorphous silicon layer
113
. Microcrystallization occurs around nucleation sites, and the nucleation sites are the locations where dopants congregate. The microcrystals inside the amorphous silicon layer tend to limit the growth of hemispherical silicon grains on the lower electrode. Therefore, the ultimate density of the hemispherical silicon grains may decrease considerably.
In other words, the longer the depositing time for the doped amorphous silicon layer
113
, the higher the probability of microcrystallization is. The higher the microcrystal density inside the amorphous silicon layer, the lower the quantity of hemispherical silicon grains on the lower electrode surfaces is. Hence, the supposed amount of increase in effective capacitative area is not actually attained.
One method of preventing the formation of too many microcrystals inside a doped amorphous silicon layer
113
is to lower the concentration of dopants during deposition. However, the doped amorphous silicon layer
113
also fills the contact opening
112
so that the source/drain region
108
is electrically connected. Therefore, too few dopants inside the doped amorphous silicon layer
113
results in a high contact resistance between the doped amorphous silicon layer
113
and the source/drain region
108
.
In light of the foregoing, there is a need to improve the method of forming a doped amorphous silicon layer so that more hemispherical silicon grains can be formed over the lower electrode surfaces of a capacitor.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide a method for forming hemispherical silicon grains on the surfaces of a doped amorphous silicon layer such that the density of silicon grains on its surfaces is not affected by microcrystallization at nuclear sites within the doped amorphous silicon layer.
In another aspect, the purpose of this invention is to provide a method for forming hemispherical silicon grains on the lower electrode surfaces of a capacitor such that contact resistance between the lower electrode and a source/drain region is lowered.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming hemispherical silicon grains on selected surfaces of a silicon layer. The method includes the steps of forming a doped polysilicon layer over a substrate, and then forming amorphous spacers on the sidewalls of the doped polysilicon layer. Thereafter, an ion implantation is carried out to transform the upper portion of the doped polysilicon into an amorphous silicon layer. Finally, hemispherical silicon grains are formed on the upper surface of the amorphous layer lying above the polysilicon layer and the exposed surface of the amorphous spacers.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4697333 (1987-10-01), Nakahara
patent: 5597741 (1997-01-01), Sakamoto et al.
patent: 5773342 (1998-06-01), Fukase
patent: 5821157 (1998-10-01), Lee et al.
patent: 5897352 (1999-04-01), Lin et al.
patent: 5915189 (1999-06-01), Sim
Chen Anchor
Chen Shih-Ching
Bowers Charles
Huang Jiawei
J C Patents
Smoot Stephen W.
United Semiconductor Corp.
LandOfFree
Method for forming hemispherical silicon grains on... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming hemispherical silicon grains on..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming hemispherical silicon grains on... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2561090