Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-10-03
2003-11-25
Thomas, Tom (Department: 2811)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S582000, C438S586000, C438S648000, C438S592000
Reexamination Certificate
active
06653225
ABSTRACT:
RELATED APPLICATION
This application relies for priority upon Korean Patent Application No. 2000-66830, filed on Nov. 10, 2000, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method therefor, and more particularly, to a gate electrode structure with an improved profile, and a method for manufacturing the same.
2. Description of the Related Art
As the degree of integration in semiconductor memory devices increases, areas occupied by separate devices, for example, a transistor, are reduced. In the transistor, hot carriers are generated in a channel region due to a short channel effect according to the reduction in area. In order to solve problems associated with the hot carrier effects, a lightly doped drain and source (LDD) transistor, in which source and drain regions are formed after forming spacers on the sidewalls of the gate electrode of the transistor and the sidewalls of a capping layer, are provided. Here, the capping layer is an insulating film formed on the gate electrode to protect the gate electrode in subsequent processing steps.
In general, a polycide, a structure with a refractory metal silicide layer formed on top of the polysilicon gate, is used to form a gate electrode. Typically, a thermal process is used to decrease the resistance of the gate electrode after forming the capping layer and the gate electrode. However, the refractory metal silicide layer becomes much larger than the capping layer during thermal expansion due to a variation in the coefficients of thermal expansion between the two materials. Accordingly, the profile of the gate electrode structure is not vertical but sloped.
Recently, a self-aligned contact hole is formed between the gate electrodes and then filled with a conductive material. As the semiconductor device is highly integrated, the slope of the sidewall of the gate electrode decreases and a sidewall spacer becomes thinner. Accordingly, the possibility of shorts between a conductive layer formed in the self-aligned contact hole and the gate electrodes substantially increases.
In order to prevent such shorts between the gate electrodes and the conductive layer, there have been attempts to increase the thickness of the spacer. However, as the thickness of the spacer increases, the distance between the gate electrodes becomes smaller. Therefore, voids are generated when the space between the gate electrode structures is filled with an interlayer insulating layer. Subsequently, voids are filled with the conductive material and undesirably connected to the conductive layer formed in an adjacent self-aligned contact hole, resulting in device failure.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a gate electrode structure, in which the slope of the profile of the gate electrode structure increases.
Accordingly, to achieve the above object, after sequentially forming a gate electrode conductive layer, for example, a polycide formed of polysilicon and a refractory metal silicide layer, and an insulating layer to form a capping layer on a semiconductor substrate, a thermal process is performed on the semiconductor substrate. The capping layer and the gate electrode are then formed by patterning an insulating layer and a conductive layer.
In another embodiment, after forming the conductive layer for the gate electrode and the insulating layer for the capping layer, the capping layer is formed by patterning the insulating layer. The thermal process is performed on the semiconductor substrate including the conductive layer. Then, the gate electrode and the spacer are formed.
According to the above-mentioned method, it is possible to skip a thermal process between a process of patterning the gate electrode and a process of forming the spacer by performing a thermal process on the conductive layer before the patterning process for forming the gate electrode. Also, it is possible to prevent the slope of the profile of the gate electrode structure from being decreased by patterning the conductive layer for the gate electrode, which is already thermally expanded. Here, that the slope of the profile of the gate electrode structure becomes decreased may mean that the slope of the side surface of the gate electrode structure is less than 80° in a peripheral region and is less than 83° in a core region.
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Vivek Jain and Dipankar, “In-Situ Stress Changes of WSi (x) Film During Polycide Process Sequence,” Proc. 7thInternational VLSI Multilevel Interconnection Conference (1990), pp.261-267.*
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Ju Byong-Sun
Kim Bong-Soo
Paik Jae-Cheol
Magee Thomas
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Thomas Tom
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