Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-02
2003-09-30
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S396000
Reexamination Certificate
active
06627494
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a flash memory and, in particular, to an improved method for forming a gate electrode of a flash memory having improved electrical properties, using a TaON film having a high dielectric constant and superior film qualities as the gate insulation film.
2. Description of the Background Art
In general, a flash electrically programmable erasable read only memory (EEPROM), which has been widely employed as a nonvolatile memory, can be electrically programmed to add data and electrically erased to remove data.
The programming operation of the EEPROM serves to increase the threshold voltage of the cell transistor by forming channel hot electrons at the drain side and accumulating the electrons in a floating gate.
Conversely, the erase operation of the EEPROM reduces the threshold voltage of the cell transistor by generating a high voltage between a source/substrate and the floating gate, and discharging the electrons that had been accumulated in the floating gate.
In order to achieve higher levels of integration of semiconductor devices, extensive efforts have been made to reduce both the cell area and the operating voltage.
Accordingly, the flash memories have tended to use a nitride-oxide (NO) or oxide-nitride-oxide (ONO) structure as the gate insulation film, rather than a general silicon oxide (SiO
2
) film.
In a process of fabricating the cell transistor for a flash memory using the NO or ONO dielectric material, the NO or ONO structure formation includes growing an oxide film on the polysilicon floating gate using a high temperature thermal oxidization method.
However, the resulting oxide film is non-uniform at the polysilicon interface of the lower floating gate, thereby increasing the thickness of an equivalent oxide film (T
ox
). As a result, the cell capacitance of the flash memory is decreased.
Therefore, in order to obtain sufficient capacitance for high capacity and high integration memory products, research and development efforts have been made to replace NO or ONO with Ta
2
O
5
to provide a higher dielectric constant.
However, Ta
2
O
5
has an unstable stoichiometry, and thus vacancy Ta atoms exist in a thin film as a result of variations in the ratio of Ta and O atoms in the deposited layer. Further carbon atoms, carbon compounds (CH
4
, C
2
H
4
, etc.) and water (H
2
O) are generated during the deposition of the Ta
2
O
5
layer by side reactions between the organic components of the organometallic precursor compound, such as Ta(OC
2
H
5
), and the O
2
(or N
2
O) gas within the LPCVD chamber. These contaminants are, in turn, incorporated into the Ta
2
O
5
film.
As a result, the leakage current of the whole cell gate electrodes is increased and the dielectric properties are degraded by the contaminants including oxygen vacancies, carbon and carbon compounds, ions and radicals remaining in the the Ta
2
O
5
film.
In order to remove such impurities from the Ta
2
O
5
film, a low temperature thermal treatment (for example, plasma N
2
O or UV-O
3
) is typically performed two or three times, thereby complicating the fabrication process. In addition, the Ta
2
O
5
film can act as an oxidizer and thus tends to form an oxide film at the interface between the Ta
2
O
5
film and the floating gate, thereby reducing the capacitance of the resulting flash memory cell gate electrode.
SUMMARY OF THE INVENTION
Accordingly, a primary object of the present invention is to provide a method for forming a gate electrode for a flash memory which can obtain a high capacitance by using a dielectric film having a high dielectric constant.
Another object of the present invention is to provide a method for forming a gate electrode for a flash memory that will improve the electric properties of the resulting cell transistor in the flash memory.
In order to achieve the above-described objects of the present invention, a method for forming a gate electrode of a flash memory comprises the steps of: providing a semiconductor substrate; forming a tunnel oxide film on the whole surface of the semiconductor substrate; forming a conductive film for a floating gate on the tunnel oxide film; forming a TaON film on the conductive film for the floating gate; forming a conductive film for a control gate on the TaON film; and forming a gate electrode, by patterning and etching the conductive film for the control gate, the TaON film, the conductive film for the floating gate and the tunnel oxide film using a gate mask.
In addition, a method for forming a gate electrode for a flash memory comprises the steps of: providing a semiconductor substrate; forming a tunnel oxide film on the whole surface of the semiconductor substrate; forming a conductive film for a floating gate on the tunnel oxide film; nitriding or nitride-oxidizing the surface of the conductive film for the floating gate, before depositing a TaON film; forming the TaON film on the nitrided or nitride-oxidized conductive film for the floating gate; nitriding or nitride-oxidizing the surface of the conductive film for the floating gate, after depositing the TaON film; crystallizing the nitrided or nitride-oxidized TaON film using a thermal treatment; forming a conductive film for a control gate on the TaON film; and forming a gate electrode, by patterning and etching the conductive film for the control gate, the TaON film, the conductive film for the floating gate and the tunnel oxide film.
REFERENCES:
patent: 6287910 (2001-09-01), Lee et al.
patent: 6291343 (2001-09-01), Tseng et al.
patent: 6303481 (2001-10-01), Park
patent: 6326282 (2001-12-01), Park et al.
patent: 6337291 (2002-01-01), Park et al.
patent: 6338995 (2002-01-01), Hwang et al.
patent: 6458645 (2002-10-01), DeBoer et al.
patent: 2001/0036703 (2001-11-01), Lee et al.
patent: 2001/0036708 (2001-11-01), Shin et al.
Ahn Byung Kwon
Joo Kwang Chul
Hynix / Semiconductor Inc.
Meier Stephen D.
Perkins Pamela
Pillsbury & Winthrop LLP
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