Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-22
2001-01-16
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S595000, C438S597000
Reexamination Certificate
active
06174776
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to forming a complementary metal oxide semiconductor, more particularly to the production of a gate contact in the complementary metal oxide semiconductor.
2. Description of the Prior Art
Generally, gate contact metal oxide semiconductor (GCMOS) will have gate contact (GC) implantation by the zero degree angle into source site only. In the fabrication process, when the polysilicon layer becomes narrower, the implant will be very aligned. Therefore, the operation for the overlay rule of GC implanting to the source region of the active area will become the major issue of the above fabrication process.
In the conventional method, and referring to
FIG. 1A
, firstly a semiconductor substrate
10
with an oxide layer
11
upon the semiconductor substrate
10
is provided. Again, as in
FIG. 1A
, defining polysilicon
12
as gate
12
is carried out.
Sequentially, as
FIG. 1B
, photoresist mask
13
is formed on top surface of oxide layer
11
and it can cover half of gate
12
. Gate contact implanting is achieved as a poor overlay region
14
, about 0.09 &mgr;m.
Then, as shown in
FIG. 1C
, source/drain is implanted as regions
15
A and
15
B. Then, annealing can be completed soon by using rapid thermal processing (RTP) at 1000° C.
Then, as shown in
FIG. 1D
, silicon nitride
16
is deposited and etched as spacer
16
upon top surface of oxide layer
11
.
Finally, as shown in
FIG. 1E
, salicide can be formed as salicilide zone
17
on top surface of gate
12
and top surface of oxide layer
11
by using rapid heating processing.
Normally, the development of quarter-micrometer CMOS devices requires so-called substrate engineering as well as drain engineering. The formation of the bulk doping profile is one of the most important technologies in the quarter-micrometer range.
However, obviously, the constructed structure of the semiconductor device by the above progress does not satisfy the requirement of the next generation. Therefore, it is necessary to develop another fabrication process in the field of the smaller size in the semiconductor industry, such as 0.18 &mgr;m.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming gate contact in the CMOS that substantially can precisely controlling the shape and area of the CMOS.
In one embodiment, a semiconductor substrate and a silicon dioxide layer are provided upon the semiconductor substrate. Then, a polysilicon layer is formed upon the oxide layer. Next, defining and etching the polysilicon layer are carried out to form a gate. Implanting upon the top surface of the silicon dioxide layer are achieved so that source/drain region is formed below and abuts the silicon dioxide layer. The source/drain region will be annealed. A spacer can be formed and abut the sidewall of the gate. A salicide is formed and overlapped upon the top surface of the gate and over the semiconductor substrate. Then, a gate contact area can be defined upon the top surface of the semiconductor substrate by using a mask that has a pattern covering approximately the half of the gate and the spacer. The half of the spacer can be removed without being covered by the mask. Finally, implanting will be completed to form gate contact in the substrate by using the salicide as an implanting mask.
REFERENCES:
patent: 5320974 (1994-06-01), Hori et al.
patent: 5399526 (1995-03-01), Sumi
patent: 5547888 (1996-08-01), Yamazaki
patent: 6004849 (1999-12-01), Gardner et al.
patent: 6004852 (1999-12-01), Yeh et al.
patent: 6017823 (2000-01-01), Shishiguchi et al.
Hao Ching-Chiao
Hsiao Chih-Yuan
Tseng Hua-Chou
Harness & Dickey & Pierce P.L.C.
Pham Long
United Microelectronics Corp.
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