Method for forming gate

Details Method for forming gate Method for forming gate

2002-09-12

2003-05-13

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06562682

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a method for forming semiconductor devices.
More particularly, the present invention relates to a method for forming a semiconductor gate.
2. Description of Related Art
In the semiconductor manufacture processes, a method for forming gates without using chemical mechanical polishing (CMP) for planarization has been proposed. Because the CMP process is not required, the gate-forming method is more cost-efficient and environmental friendly. In the gate-forming method, a cap layer is formed on the gate electrode and a high density plasma (HDP) oxide layer is deposited over the substrate and between the gate electrodes. A portion of the HDP oxide layer is removed by HF until the cap layer is exposed. During the step of removing the cap layer, the extra HDP oxide layer on the gate is also removed to obtain a HDP oxide layer with a planar surface. As the device dimension shrinks, the line-widths for the gates become shorter in order to maintain the lengths of channels. Therefore, a wider polysilicon layer is formed at an upper portion of the gate to increase the upper surface, thereby increasing the process window and reducing the resistance.
Following the prior art processes, defects formed at the interface between the HDP oxide layer and the gate can cause through holes down to the substrate if misalignment occurs during forming the wider polysilicon layer, which results in single bit failure and deteriorates reliability. Such failures suffering from misalignment and decreased distances between gates further reduce the gate coupling ratio (GCR).
SUMMARY OF INVENTION
The present invention provides a method for forming a semiconductor gate, which can prevent single bit failure resulting from defects at the interface between the HDP dielectric layer and the polysilicon gate.
Accordingly, the present invention provides a method for forming a semiconductor gate, which can increase reliability and increase gate coupling ratio.
Moreover, the method of the present invention relates to a method for forming a semiconductor gate, which can provide larger misalignment window for the photolithography process toward defining the gate.
As embodied and broadly described herein, the invention provides a method for forming a semiconductor gate. Because the oxide spacers (or the remained oxide layer) located on sidewalls of the recess can isolate the interface between the HDP dielectric layer and the polysilicon gate being exposed, thereby preventing single bit failure resulting from defects at the interface between the HDP dielectric layer and the polysilicon gate. Therefore, reliability of the memory is enhanced. Moreover, since the oxide spacer (or the remained oxide layer) protects a portion of the underlying conductive layer, the misalignment window for defining the gate can be enlarged.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5907775 (1999-05-01), Tseng
patent: 5923976 (1999-07-01), Kim
patent: 6194300 (2001-02-01), Hung et al.
patent: 6271090 (2001-08-01), Huang et al.

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